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Visitor canopusgao
Visitor
168 Views
Registered: ‎07-11-2017

XAPP585 TX Issue

Hi Guys

I'm using XAPP585 on a ZYNQ 7000 device.

I'm trying to send video signal from FPGA to Panel throught LVDS.

It works in the simulation.

1.PNG

But it fails on board test. And I got no right signal on any LVDS port in Oscilloscope.

I also tried to debug the serial signal before OBUFDS with ILA.

2.PNG

However, it failed at writing bitstream because of the unrounted net.

7.PNG

And the following are my constraints.

##Clock signal
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports clk]
create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports clk]

##Pmod Header JC
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVDS_25} [get_ports {data_out_p1_p[1]}]
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVDS_25} [get_ports {data_out_p1_n[1]}]
set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVDS_25} [get_ports {data_out_p1_p[2]}]
set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVDS_25} [get_ports {data_out_p1_n[2]}]
set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVDS_25} [get_ports {data_out_p1_p[0]}]
set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVDS_25} [get_ports {data_out_p1_n[0]}]
set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVDS_25} [get_ports clk_out_p1_p]
set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVDS_25} [get_ports clk_out_p1_n]


##Pmod Header JD
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVDS_25} [get_ports {data_out_p1_p[3]}]
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVDS_25} [get_ports {data_out_p1_n[3]}]

 

Is there anyway that I can debug this issue?

Thanks

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1 Reply
Community Manager
Community Manager
123 Views
Registered: ‎08-08-2007

Re: XAPP585 TX Issue

Hi @canopusgao 

 

That OQ cannot be routed internally.

Firstly I would suggest trying a simple testcase. Just try to forward out your clock through those IOB pair with an ODDR going to the OBUFDS. That will help narrow down if there is an issue with the board or the design. When you forwarding out with the ODDR connect the D inputs to 1 and 0 and the CLK to your clock.

If the ODDR works and you can see clock pattern on the output the issue is likely with the design. Next then I would suggest you put the ILA on the inputs to the OSERDES which you can connect and see if the input to the OSERDES is correct.

If you cannot see the ODDR output the clock I would take a look at the board, what is the bank powered to? Does the IOSTANDARD in the design match? In the oscillscope setup correctly? Can you see the input clock to the FPGA correctly with the scope. 

 

Sandy

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