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Contributor
Contributor
728 Views
Registered: ‎06-16-2017

ZYNQ differential clock input

Hi,

 

I have an AFE interfaced to a ZYNQ 007S.  The output of the AFE has LVDS clock and data.

 

My question:

 

Can I use the following for the clock and data in the FPGA?

 

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
//  clock
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
    IBUFDS #
    (
        .DIFF_TERM      ( "FALSE"   ),      // Differential Termination
        .IBUF_LOW_PWR   ( "FALSE"    ),      // Low power="TRUE", Highest performance="FALSE" 
        .IOSTANDARD     ( "LVDS_25" )       // Specify the input I/O standard
    )
    IBUFDS_clock
    (
        .O              ( rxclk_out ),      // Buffer output
        .I              ( clkin1_p  ),      // Diff_p buffer input (connect directly to top-level port)
        .IB             ( clkin1_n  )       // Diff_n buffer input (connect directly to top-level port)
    );


////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
//  Data input 0
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
    IBUFDS #
    (
        .DIFF_TERM      ( "FALSE"   ),      // Differential Termination
        .IBUF_LOW_PWR   ( "FALSE"    ),      // Low power="TRUE", Highest performance="FALSE" 
        .IOSTANDARD     ( "LVDS_25" )       // Specify the input I/O standard
    )
    IBUFDS_D0
    (
        .O              ( din_0     ),      // Buffer output
        .I              ( din_p[0]  ),      // Diff_p buffer input (connect directly to top-level port)
        .IB             ( din_n[0]  )       // Diff_n buffer input (connect directly to top-level port)
    );

Thanks,

Dan

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4 Replies
Moderator
Moderator
713 Views
Registered: ‎04-18-2011

Re: ZYNQ differential clock input

yes this will work fine. 

 

You just need to be careful that you lock the clock to a Clock Capable input. 

 

You can check the Clocking UG for more 

 

Keith 

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Contributor
Contributor
673 Views
Registered: ‎06-16-2017

Re: ZYNQ differential clock input

Hi Keith,

 

Thanks for the reply.  I've since learned that I need to use both edges of the clock to clock the data into the FPGA.  I tried an always @ (posedge clk or negedge clk), but it wouldn't synthesize.  Any suggestions?

 

Thanks,
Dan

 

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Moderator
Moderator
669 Views
Registered: ‎04-18-2011

Re: ZYNQ differential clock input

You need to use an IDDR in this case. 

 

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Don’t forget to reply, kudo, and accept as solution.
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Contributor
Contributor
662 Views
Registered: ‎06-16-2017

Re: ZYNQ differential clock input

Hi Keith,

 

I looked at the macro for the IDDR.  It looks like it uses the p/n clock and will give me a 2-bit parallel output.  However, I'm not sure how to clock those bits into a shift register.  Would I still use the IBUFDS to recover the clock for internal use and do something like this:

 

sreg <= {Q0,Q1,sreg[6:1]};

 

Thanks,
Dan

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