03-20-2017 10:36 PM
Hi I have encrypted my design files using IEEE 1735 encryption and its successfully done and but am able to see the hierarchy of my design.so can i know how to prevent the visibilty of the design hierearchy??
03-20-2017 11:39 PM
03-21-2017 01:22 AM
I am not sure about what you can do. All the options are in UG1118 (link) p88. I have never tried all but it seems to be the child_visibility option. Did you try with delegated for synthesis?
Hope that helps,
03-21-2017 01:34 AM
I Think child_visibility works only when the parent module is protected and child module is unprotected and what actions has to be taken to child module is defined by child_visibility...
03-21-2017 01:38 AM
Did you try it?
I don't think there is more parameters available than in the UG...
03-21-2017 01:57 AM
I will give a try but as per ug1118 when you see the child_visibility parameter it is applicable in simulation,synthesis and implementation but i have a doubt that how can i define this parameter particularly in simulation or synthesis or implemenation can you tell me some syntax.
03-21-2017 02:04 AM
To have it only in synthesis, it should be something like:
`pragma protect control child_visibility = (activity==simulation)? “allowed” : “delegated”
You should use the example from UG1118 (p90) for help
03-21-2017 02:35 AM
I don't really know the standard so it is maybe not possible. Could you try:
`pragma protect control child_visibility = “delegated”
`pragma protect control runtime_visibility = “delegated”
03-21-2017 02:37 AM
03-21-2017 02:47 AM
03-21-2017 03:21 AM
Then if it is not working that means that there is no option to change the hierarchy names
03-21-2017 10:21 PM
Hi florent am not really worried about the name changes of the design sources i need to just make the hierarchy invisible.