UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
4,199 Views
Registered: ‎12-25-2015

how to minimize timing problem in vivado?

Jump to solution

Hi guys

I have some problems with timing and I don't how I can fix them. I have totally confused. could you please guide to solve this problem?

I am going to receive a HD video stream and write it in a ddr3 sdam. I am using vivado version 2015.4 and my chip family is Kintex7.

these are my timing report:

report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
WARNING: [Timing 38-164] This design has multiple clocks. Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
WARNING: [Timing 38-127] No common period was found between clocks clk_pll_i {rise@0ns fall@6.25ns period=12.5ns} and rxusrclk {rise@0ns fall@3.333ns period=6.667ns} in 1000 cycles.
Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
| Date : Mon Oct 31 16:50:55 2016
| Host : KAVIANATHAR-PC running 64-bit Service Pack 1 (build 7601)
| Command : report_timing
| Design : kc705_sdi_demo
| Device : 7k160t-ffg676
| Speed File : -2 PRODUCTION 1.12 2014-09-11
------------------------------------------------------------------------------------

Timing Report

Slack (VIOLATED) : -1.314ns (required time - arrival time)
Source: SDI1/system_i/system_i/proc_sys_reset_0/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]/C
(rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.250ns period=12.500ns})
Destination: SDI1/reset_reg/D
(rising edge-triggered cell FDRE clocked by rxusrclk {rise@0.000ns fall@3.333ns period=6.667ns})
Path Group: rxusrclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 0.005ns (rxusrclk rise@100.005ns - clk_pll_i rise@100.000ns)
Data Path Delay: 1.571ns (logic 0.236ns (15.024%) route 1.335ns (84.976%))
Logic Levels: 0
Clock Path Skew: 0.550ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.272ns = ( 101.277 - 100.005 )
Source Clock Delay (SCD): 0.722ns = ( 100.722 - 100.000 )
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.207ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.123ns
Phase Error (PE): 0.136ns
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_pll_i rise edge)
100.000 100.000 r
P23 0.000 100.000 r clk_in1 (IN)
net (fo=0) 0.000 100.000 SDI1/system_i/system_i/clk_wiz_0/inst/clk_in1
P23 IBUF (Prop_ibuf_I_O) 1.498 101.498 r SDI1/system_i/system_i/clk_wiz_0/inst/clkin1_ibufg/O
net (fo=1, routed) 1.081 102.579 SDI1/system_i/system_i/clk_wiz_0/inst/clk_in1_system_clk_wiz_0_0
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-7.249 95.330 r SDI1/system_i/system_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.781 97.111 SDI1/system_i/system_i/clk_wiz_0/inst/clk_out1_system_clk_wiz_0_0
BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 97.204 r SDI1/system_i/system_i/clk_wiz_0/inst/clkout1_buf/O
net (fo=1, routed) 1.598 98.802 SDI1/system_i/system_i/mig_7series_0/u_system_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.077 98.879 r SDI1/system_i/system_i/mig_7series_0/u_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3
net (fo=1, routed) 1.139 100.018 SDI1/system_i/system_i/mig_7series_0/u_system_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out
BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.103 100.121 r SDI1/system_i/system_i/mig_7series_0/u_system_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O
net (fo=1, routed) 0.773 100.894 SDI1/system_i/system_i/mig_7series_0/u_system_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT)
-3.443 97.451 r SDI1/system_i/system_i/mig_7series_0/u_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT
net (fo=1, routed) 1.775 99.226 SDI1/system_i/system_i/mig_7series_0/u_system_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 99.319 r SDI1/system_i/system_i/mig_7series_0/u_system_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O
net (fo=52868, routed) 1.403 100.722 SDI1/system_i/system_i/proc_sys_reset_0/U0/slowest_sync_clk
SLICE_X40Y87 FDRE r SDI1/system_i/system_i/proc_sys_reset_0/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X40Y87 FDRE (Prop_fdre_C_Q) 0.236 100.958 r SDI1/system_i/system_i/proc_sys_reset_0/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]/Q
net (fo=15, routed) 1.335 102.293 SDI1/Res
SLICE_X41Y87 FDRE r SDI1/reset_reg/D
------------------------------------------------------------------- -------------------

(clock rxusrclk rise edge)
100.005 100.005 r
BUFGCTRL_X0Y16 BUFG 0.000 100.005 r BUFGRX1/O
net (fo=2363, routed) 1.272 101.277 SDI1/rx1_usrclk
SLICE_X41Y87 FDRE r SDI1/reset_reg/C
clock pessimism 0.000 101.277
clock uncertainty -0.207 101.070
SLICE_X41Y87 FDRE (Setup_fdre_C_D) -0.091 100.979 SDI1/reset_reg
-------------------------------------------------------------------
required time 100.979
arrival time -102.293
-------------------------------------------------------------------
slack -1.314

 

 and these are some snapshot of the report:

im1.PNG

 

im2.PNG

 

im3.PNG

 

im4.PNG

 

thanks.

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
7,585 Views
Registered: ‎05-24-2013

Re: how to minimize timing problem in vivado?

Jump to solution

Hi,

 

Check the warning you get. Especially this one:

 

 

WARNING: [Timing 38-164] This design has multiple clocks. Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

 

 

If your clock domains are not related to each other, then you have to seperate them like this:

 

 

set_clock_groups -asynchronous  -group [get_clocks clk_fpga_0] \
                                -group [get_clocks clk_fpga_1] \

 

 

Check the clocks present in your design and seperate them as shown above. Here, clk_fpga_0 is my first domain and clk_fpga_1 is my second domain. 

 

 

Another thing I would suggest is to avoid asynchronous resets. Do not write something like:

 

if(reset = '1') then
     a <= '0';
elsif(rising_edge(clk)) then
     a <= b;
end if;

Instead write:

 

if(rising_edge(clk)) then
     if(reset = '1') then
         a <= '0';
     else
         a <= b;
     end if;
end if;
2 Replies
Highlighted
Adventurer
Adventurer
7,586 Views
Registered: ‎05-24-2013

Re: how to minimize timing problem in vivado?

Jump to solution

Hi,

 

Check the warning you get. Especially this one:

 

 

WARNING: [Timing 38-164] This design has multiple clocks. Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

 

 

If your clock domains are not related to each other, then you have to seperate them like this:

 

 

set_clock_groups -asynchronous  -group [get_clocks clk_fpga_0] \
                                -group [get_clocks clk_fpga_1] \

 

 

Check the clocks present in your design and seperate them as shown above. Here, clk_fpga_0 is my first domain and clk_fpga_1 is my second domain. 

 

 

Another thing I would suggest is to avoid asynchronous resets. Do not write something like:

 

if(reset = '1') then
     a <= '0';
elsif(rising_edge(clk)) then
     a <= b;
end if;

Instead write:

 

if(rising_edge(clk)) then
     if(reset = '1') then
         a <= '0';
     else
         a <= b;
     end if;
end if;
Xilinx Employee
Xilinx Employee
4,150 Views
Registered: ‎07-31-2012

Re: how to minimize timing problem in vivado?

Jump to solution
It is not a straightforward answer. To understand the reports and help you get a permanent solution, here are few links to help you read and start on timing closure

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug903-vivado-using-constraints.pdf

http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf#nameddest=TimingClosure

https://www.xilinx.com/video/hardware/analyzing-implementation-results.html
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.