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narendrandesainath@gmail.com

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10-06-2018 05:36 AM

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10-06-2018

Hello,

I am trying to write RTL code for FIR filter, in that 2 variables are there i.e **k** and **n. **the n is varying from 0 to 1023 and k is varying from 0 to 758. so because of two variable i am unable write code for it, so any one can suggest to write a code for below convolution equation.

y(n)=x[n]*h[n];

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dgisselq

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10-06-2018 11:06 AM

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Registered:
05-21-2015

I've dealt with this problem from several different contexts on ZipCPU.com. You can read my first article about building such a filter at the system clock rate here, or another similar article (with a better design and lower latency) here. There's also an article on how to test that such a filter works in general, a test report for said filters, and even two other versions appropriate for when the data rate is much slower than the system clock rate: both for a straight FIR as well as for a symmetric FIR filter.

Hopefully those will help you along your way. If you like the site, you can find other articles discussing logic PLL generation, interpolation both linear and quadratic, cordic's, FFT's, and more here.

Dan

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u4223374

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10-06-2018 06:01 AM - edited 10-06-2018 06:25 AM

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04-26-2015

Re: how to write a verilog code for convolution

This would be really easy in HLS...

In any case, you're going to have to make some decisions on the trade-off between performance and resource usage. The straightforward approach to this (it's possible that an FFT-based one would be better) will require at least 1024*759 = 777216 multiply operations, which is definitely impossible to do in a combinational way on any current FPGA. Doing one n value at a time will still cost 759 multiply operations. If they're fixed-point this is achievable on a moderately large FPGA, but it's going to be a substantial chunk of the total resources - you won't be able to do many other DSP-intensive tasks on the same chip.

Going the other way, if you only want to do one multiply per cycle then it'll be pretty cheap (even if that has to be a floating-point multiply) - but it will take 777,216 (or a few more) cycles to generate the complete output.

deeksha@f7

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10-06-2018 08:44 AM

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05-14-2018

Re: how to write a verilog code for convolution

dgisselq

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10-06-2018 11:06 AM

1,733 Views

Registered:
05-21-2015

I've dealt with this problem from several different contexts on ZipCPU.com. You can read my first article about building such a filter at the system clock rate here, or another similar article (with a better design and lower latency) here. There's also an article on how to test that such a filter works in general, a test report for said filters, and even two other versions appropriate for when the data rate is much slower than the system clock rate: both for a straight FIR as well as for a symmetric FIR filter.

Hopefully those will help you along your way. If you like the site, you can find other articles discussing logic PLL generation, interpolation both linear and quadratic, cordic's, FFT's, and more here.

Dan

narendrandesainath@gmail.com

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10-08-2018 02:53 AM

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10-06-2018

Re: how to write a verilog code for convolution

dgisselq

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10-08-2018 04:27 AM

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Registered:
05-21-2015

Re: how to write a verilog code for convolution

Didn't I just do that?

Dan