09-10-2018 05:22 AM - edited 09-11-2018 07:05 AM
Dear PCIe gurus,
I'm using xczu5ev-fbvb900-1-e FPGA device from Zynq Ultrascale+ MPSoC family.
In my system I have two PCIe Gen 3 4-lane IP cores connected with each other:
1) AXI Bridge for PCIe Gen3 IP Core (AXI Bridge mode, PG194) configured as a Root Port
2) DMA/Bridge Subsystem for PCIe in DMA mode (PG195) configured as End Point.
My Xilinx design project is created in the following way: I took RP part of design example of 1) and EP part of design example of 2) and connected them together. Consequently, everything is happening on the RTL level, there no any connection with the PS part.
Now, after PCIe link is UP, there is a configuration process occuring on the RP side (through s_axi_ctl_* axi control interface) that consists of writing into the following registers:
set_add <= #TCQ 28'h0000018; set_add <= #TCQ 28'h00000D4; set_add <= #TCQ 28'h0100010; set_add <= #TCQ 28'h0100014; set_add <= #TCQ 28'h0100018; set_add <= #TCQ 28'h0100030; set_add <= #TCQ 28'h0100010; set_add <= #TCQ 28'h0100014; set_add <= #TCQ 28'h0100018; set_add <= #TCQ 28'h0100030; set_add <= #TCQ 28'h0100070; set_add <= #TCQ 28'h0100004; set_add <= #TCQ 28'h0001148; set_add <= #TCQ 28'h000120C; set_add <= #TCQ 28'h0000004; set_add <= #TCQ 28'h0100004;
the following set of data:
set_data <= #TCQ 32'h00010100; set_data <= #TCQ 32'h00000C80; set_data <= #TCQ 32'hFFFFFFFF; set_data <= #TCQ 32'hFFFFFFFF; set_data <= #TCQ 32'hFFFFFFFF; set_data <= #TCQ 32'hFFFFFFFF; set_data <= #TCQ 32'h80000000; set_data <= #TCQ 32'h10000000; set_data <= #TCQ 32'h20000000; set_data <= #TCQ 32'h80000001; set_data <= #TCQ 32'h00000041; set_data <= #TCQ 32'h00000006; set_data <= #TCQ 32'h00000001; set_data <= #TCQ 32'h80000000; set_data <= #TCQ 32'h00100007; set_data <= #TCQ 32'h00100007;
Once this process is finished, I initiate data transfer from EP side to RP side through C2H channel (in AXI Stream mode with descriptor bypass).
Everything seems to be OK on the EP side, data are sent from EP side because when polling the C2H status register (0x04) I can read the value 32'h00000006 (descriptor_completed and descriptor_stopped bits set). Furthermore, I can see that descriptor count number increases by reading C2H Channel Completed Descriptor Count register (0x48).
However, I am unable to see the data on AXI master interface (m_axib_*) on RP side. Do you guys have any idea what I am missing here?
When taking a closer look into my simulation, I noticed that data sent from EP side through AXI-Stream interface, appear on axis_rq port of EP side as well as on axis_cq port on RP side.
This implies that data are properly sent and received on the RP part. The only trouble now is why I don't see them on axi master interface (m_axib_*) on the RP side !?
What I also noticed is that the master reponse ready signal (m_axi_bready) from axi master interface (output of the IP core) is always on logic level '0'. This tells me something wrong is happening inside AXI Bridge PCIe RP IP.
Any ideas ?
Thanks in advance for your time and effort.
09-19-2018 07:58 AM
Could you please PM your email address? I would like to take a look at the simulation waveform with signals logged. I can send you an EZMove to transmit it over.
09-20-2018 04:43 AM