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Participant zguo
Registered: ‎05-19-2017

Bus interface definitions for PCIe4

I have an IP block that implements the various control interfaces to the ultrascale+ PCIe4 IP. Out of a desire to not have to route every single signal between my ip and the pcie ip in the block design, I'm trying to organize the various ports into their respective buses. This worked fine for some of them, like the msi, mesg_tx, and mesg_rcvd. Others however I'm not seeing the interface definitions for them in the IP packager. Or rather, I am not seeing any pcie4 interfaces. The ones above that I mentioned I could get working were instead using pcie3 defined interfaces or even a 7series defined interface. That being the case, is there a way for me to tell Vivado or the IP packager to look for interfaces in additional places? Or wherever the pcie4 interfaces are actually stored? They're obviously there since the IP block of the pcie4 IP itself is using them, they just don't seem to be exposed.


This is in Vivado 2017.1.

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Visitor dnitecki
Registered: ‎05-29-2018

Re: Bus interface definitions for PCIe4

I had the same problem in Vivado 2018.1 and I found a workaround.

In the IP Packager when I tried to make a custom component with mating interfaces to control PCIe4 IP Core, I couldn't do it because in the IP Packager PCIe4 control interfaces were missing, e.g.:
VLNV xilinx.com:display_pcie4:pcie4_cfg_mgmt_rtl:1.0
VLNV xilinx.com:display_pcie4:pcie4_cfg_pm_rtl:1.0

The only option left for me was to connect every signal in all interfaces one by one. It would be very time consuming.


To make a workaround I copied an “interfaces” folder from the PCIe4 IP Core Vivado installation folder to my project:

I made modifications to the interfaces as follows:
for “*_rtl.xml” files I added some character, e.g. 'm', at the beginning of the “spirit:busType->spirit:library” parameter value;
For other xml files I changed “spirit:library” value parameter accordingly by adding a character, e.g. 'm' at the beginning of the parameter value.



Then I added changed interfaces folder to my project by Settings->IP->Repository and it worked!

Now I can see all pcie4 interfaces in the IP Packager.



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