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Conflicting pin contraints with "32-bit Initiator/Target for PCI (7-Series)" IP-Core

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Adventurer
Posts: 80
Registered: ‎04-13-2010

Conflicting pin contraints with "32-bit Initiator/Target for PCI (7-Series)" IP-Core

Hi,

 

I want to implement a "32-bit Initiator/Target for PCI (7-Series)" IP-Core (Yes, the old stuff. For us it is still alive and kicking) into an Artix-7 XC7A15TFTG256. I'm using Vivado 2017.3.

 

I had to open the example design to get a constraints file for the core. This .xdc places the complete PCI interface into the bank 14, leaving no unoccupied pins in this bank. But bank 14 is also used for configuration, resulting in a bunch of conflicting pins. 

 

Besides that, the pinout is fubar in a way that makes it very hard to layout the PCI interface on a PCB, if even possible.

 

UG262 tells me to "not modify the provided constraint’s file pin placement". Together this is making an implementation practical impossible.

 

1. Is the restriction to "not modify the provided constraint’s file pin placement" still valid (it is from 2012...)? Or can I change pin locations when necessary?
2. Can I somehow get a constraints file that has pin locations that are possible to implement?

 

Regards,

hirschdaumen