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Visitor partieri
Registered: ‎04-03-2019

DMA for PCI Express (PCIe) Subsystem IP Vivado 2018.3 KC705 EVB

I have a problem with DMA/Bridge Subsystem for PCI Express v4.1 and KC705 evaluation board.

I configure the IP with only AXI DMA interface and connect it to external DDR but i can't write anything from the Host.

I try to connect the second BAR DMA Bypass Interface and connect it to the external DDR and it works, but the AXI DMA interface connected to the bram controller still doesn't work.

So the fist BAR AXI DMA Interface doesn't work and the second BAR DMA Bypass Interface works.

What kind of problems are there with the first BAR AXI DMA Interface?

Why it doesn't work?

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Xilinx Employee
Xilinx Employee
Registered: ‎07-26-2012

Re: DMA for PCI Express (PCIe) Subsystem IP Vivado 2018.3 KC705 EVB

Is the problem happening on a real hardware or simulation? If it is in an actual board, can you try simulating the design? And also, is the driver a Xilinx provided driver? Or is it your own driver? If your drivere is used, can you try the driver in

https://github.com/Xilinx/dma_ip_drivers/tree/master/XDMA/linux-kernel ?

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