UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer babu_r
Observer
743 Views
Registered: ‎07-02-2017

FPGA configuration and PERST_N deassertion (PCIe, Gen2, endpoint)

Hi,

Using Artix-7, 35T, CSG325 device and our design has to support PCIe, Gen2 (endpoint). Thus, using Xilinx IP core for PCIe..

 

In our system, the FPGA is getting configured in 105mS which is within the allowed time of 120mS. ie.PCIe host will deassert the reset within 100mS and expects the endpoint to respond within 20mS.

 

My doubts is Does FPGA needs to be configured inside 100mS (ie., before PCIe host deasserts the Reset (PREST_N))? Not sure either IP core needs to see PREST_N as LOW before it is taken HIGH by the host.

 

As per my understanding from below statement referred at pg054 (Logicore IP product guide), it is acceptable if FPGA configured inside 120mS and ready to link train. It doesn't need to see RESET as LOW. All the IP core need is PREST_N to be deasserted and FPGA to be ready to link train within 20mS from deassert. Please clarify..

 

Below statement is from pg054, page-154

The PCI Express Specification states that PERST# must deassert 100 ms after the power good of the systems has occurred, and a PCI Express port must be ready to link train no more than 20ms after PERST# has deasserted. This is commonly referred to as the 100 ms boot time requirement.

 

Thank you - Babu

 

0 Kudos
4 Replies
Xilinx Employee
Xilinx Employee
685 Views
Registered: ‎12-10-2013

Re: FPGA configuration and PERST_N deassertion (PCIe, Gen2, endpoint)

Hi @babu_r,

 

We do require that post-configuration, the PCIe core does get reset via a PERST_N.  So if the system is taking the core out of reset prior to configuration completing, this could lead to instability in the GTs and locks.  You could potential create a logical assertion of reset / PERST on the FPGA, or look at speeding up the configuration clocks or compressing the bitstream to speed up load.  

 

The information copied from the document is informative as to the PCIe specification.   That being said, there are many, many systems to that require this in practice.  Also, if you are in closed system, and control the reset sequence, the upstream could be held in reset while the FPGA loads, or a reset could be issued.

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Observer babu_r
Observer
678 Views
Registered: ‎07-02-2017

Re: FPGA configuration and PERST_N deassertion (PCIe, Gen2, endpoint)

Hi Bethe,

 

What is the duration to which the core to be held in RESET by PERST_N? This decides the time by which configuration to be completed. Without considering the RESET duration, we know the core to get configured within 100mS. But now when Reset is accounted then configuration time will get reduced. So, please let us know the minimum required duration that the core has to see the reset via PERST_N..

 

Thank you - Babu

0 Kudos
Observer babu_r
Observer
615 Views
Registered: ‎07-02-2017

Re: FPGA configuration and PERST_N deassertion (PCIe, Gen2, endpoint)

Hi Bethe,

 

Do you have any update, please?

 

Thank you - Babu

0 Kudos
Xilinx Employee
Xilinx Employee
574 Views
Registered: ‎12-10-2013

Re: FPGA configuration and PERST_N deassertion (PCIe, Gen2, endpoint)

Hi @babu_r,

 

We recommend asserting PERST for 16 clock cycles.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------