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GT wizard sub ip reconfig

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Visitor
Posts: 3
Registered: ‎09-14-2015

GT wizard sub ip reconfig

Dear Community,

I am trying to configure the "UltraScale FPGA Gen3 Integrated Block for PCI Express" IP for our custom Kintex ultrascale board in Vivado. For our design the exact GT position and the reference clock source must be set manually.

To configure these parameters I am planning to set the proper parameters in the gt_wizard sub IP, thus I have selected the "Include GT Wizard in example design" option in the PCIe IP config GUI.

 

After clicking to the generate output product on the IP node I get the following errors:

 

ERROR: [Common 17-69] Command failed: Failed to get scope property. Unknown property 'ipbom'
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file '/opt/Xilinx/Vivado/2017.1/data/ip/xilinx/pcie3_ultrascale_v4_3/ttcl/gtwizard_top_v.ttcl':

ERROR: [Common 17-69] Command failed: Failed to get scope property. Unknown property 'ipbom'
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'pcie3_ultrascale_3'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'pcie3_ultrascale_3'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block pcie3_ultrascale_3

 

Without setting the "Include GT Wizard in example design" option the output products are generated successfully.

 

I get these error messages both in Vivado version 2017.1 and 2017.2

The device part is: xcku040-ffva1156-2-e


Please help me, how can I get rid of these error messages and configure the IP properly.

 

Regards,
T. Peto

 

Xilinx Employee
Posts: 2,291
Registered: ‎02-16-2010

Re: GT wizard sub ip reconfig

This looks to be a known issue.
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