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Explorer
Explorer
218 Views
Registered: ‎04-12-2012

Generating MSI interrupts

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Hello,

In my design I'm using the PCIe DMA Subsystem:

https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_1/pg195-pcie-dma.pdf

Page 117 shows that 4 different types of interrupt mechanisms are supported.

 

Question:

Suppose I want the FPGA logic to invoke an MSI or an MSI-X interrupt at the host. 

What's the correct process for that ?

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Xilinx Employee
Xilinx Employee
141 Views
Registered: ‎08-02-2007

回复: Generating MSI interrupts

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yes if both 1 and 2 are correctly finished 

that means the MSI func is enabled and not masked,the bus master bit is on and  the vector is set correctly

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Xilinx Employee
Xilinx Employee
165 Views
Registered: ‎08-02-2007

回复: Generating MSI interrupts

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1The host will need to first config the MSI /MSIX registers in the config space.

For MSIX , the MSIX table will be filled out by the host too

2 driver needs to config the DMA IRQ  registers in  Table 2-77: IRQ Block Register Space

3 channel or user interrupt be triggered by DMA engine or user 

 

 

 

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Explorer
Explorer
150 Views
Registered: ‎04-12-2012

回复: Generating MSI interrupts

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3 channel or user interrupt be triggered by DMA engine or user 

So if the user fpga application raises one of the bits of the usr_irq_req vector - this will raise an MSI interrupt ?

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Xilinx Employee
Xilinx Employee
142 Views
Registered: ‎08-02-2007

回复: Generating MSI interrupts

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yes if both 1 and 2 are correctly finished 

that means the MSI func is enabled and not masked,the bus master bit is on and  the vector is set correctly

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Explorer
Explorer
134 Views
Registered: ‎04-12-2012

回复: Generating MSI interrupts

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