UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer dmitril
Observer
45 Views
Registered: ‎01-17-2018

How to ensure strong ordering when writing to RAM and FPGA registers via PCIe?

Hi,
I am trying to ensure strong ordering when accessing Zynq-7000 via PCIe.
My Zynq is an endpoint using AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.9.
It has 2 Bars: first exposes a RAM region (RAM is attached to Zynq on a KRM module), second Bar exposes FPGA registers.
PCIe root complex first writes data to RAM, then writes a flag to FPGA register, which causes IRQ.
Software on Zynq read that flag from FPGA register (using AXI) and then reads RAM.
Question is whether it is possible that RAM write is completed after FPGA register write and whether software will read stale data.
I read "Transaction Ordering for PCIe" in pg055-axi-bridge-pcie.pdf, but it does not appear to address this case.
Thank you

0 Kudos