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Explorer
Explorer
3,848 Views
Registered: ‎12-02-2012

MSI support basics

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Reading PG054 on the section about MSI support (page 140) and just wanted to double check my understanding. This seems to suggest that, assuming I do not have multi-vector support, the only thing my user logic needs to do to signal an interrupt is to assert cfg_interrupt and wait until cfg_interrupt_rdy is asserted. Everything else, such as generating the actual TLP write message, is done by the IP core itself. Is that correct?

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-25-2015

Re: MSI support basics

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Hi @zwabbit,

 

Yes your understanding is correct..But please make sure everything i mentioned is set

 

1) Enable ‘Bus Master Enable’ bit in the Root Port by adding the code shown in Figure 9, in board.v.

2) In dsport/pci_exp_usrapp_tx.v, make sure Bus Master Enable bit in the Endpoint Command Register.

3) Add the following in dsport/pci_exp_usrapp_tx.v to configure the MSI registers

4) For requesting interrupt service from the user application to the core. In order to generate an MSI, user should assert cfg_interrupt and provide Message data on cfg_interrupt_di. This can be done by using Verilog force-release statements

 

Refer attachment for ease of reference

 

Note: Cross-check whether MSI control register has MSI enable bit set and programming has taken effect. Moreover In order to enable MSI in kernel, kernel should be built with CONFIG_PCI_MSI macro set to 1.

 

Thanks,

Sethu

MSI 1.JPG
MSI 2.JPG
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Xilinx Employee
Xilinx Employee
3,815 Views
Registered: ‎08-01-2008

Re: MSI support basics

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check this document it will give you some more details
https://www.xilinx.com/Attachment/Xilinx_Answer_58495_PCIe_Interrupt_Debugging_Guide.pdf
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
7,240 Views
Registered: ‎11-25-2015

Re: MSI support basics

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Hi @zwabbit,

 

Yes your understanding is correct..But please make sure everything i mentioned is set

 

1) Enable ‘Bus Master Enable’ bit in the Root Port by adding the code shown in Figure 9, in board.v.

2) In dsport/pci_exp_usrapp_tx.v, make sure Bus Master Enable bit in the Endpoint Command Register.

3) Add the following in dsport/pci_exp_usrapp_tx.v to configure the MSI registers

4) For requesting interrupt service from the user application to the core. In order to generate an MSI, user should assert cfg_interrupt and provide Message data on cfg_interrupt_di. This can be done by using Verilog force-release statements

 

Refer attachment for ease of reference

 

Note: Cross-check whether MSI control register has MSI enable bit set and programming has taken effect. Moreover In order to enable MSI in kernel, kernel should be built with CONFIG_PCI_MSI macro set to 1.

 

Thanks,

Sethu

MSI 1.JPG
MSI 2.JPG
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