UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor vish6353
Visitor
1,105 Views
Registered: ‎06-20-2018

PCIE core is not detecting if I add DDR3 controller in the design

hi,

      If I add DDR3(MIG with 2 controller) to the design then the  alrady existing pcie(gen2 ,X4) core can not be detected by the Processor.DDR calib_complete is also coming high. Artix 7 FPGA is the development platform.I tried reboot,reset through command.if I remove 1 controller it is detecting randomly(eg:gen2 X1, gen1 X4,etc..). please help.

0 Kudos
16 Replies
Moderator
Moderator
1,052 Views
Registered: ‎02-16-2010

Re: PCIE core is not detecting if I add DDR3 controller in the design

Whether the failing design is closing timing?
Are there any unconstrained paths in the design? You can check the unconstrained paths by opening the implemented design and running the timing analysis.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Visitor vish6353
Visitor
1,018 Views
Registered: ‎06-20-2018

Re: PCIE core is not detecting if I add DDR3 controller in the design

There is no failing constraints.all the timing constraints met.and iam using ISE 14.7 for designing it.

Design.JPG
0 Kudos
Moderator
Moderator
1,006 Views
Registered: ‎02-16-2010

Re: PCIE core is not detecting if I add DDR3 controller in the design

The snapshot does not show the timing result. Can you show the timing analysis result?
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Visitor vish6353
Visitor
970 Views
Registered: ‎06-20-2018

Re: PCIE core is not detecting if I add DDR3 controller in the design

 

     Here I have attached the ISE timing analysis report(TWX,TWR).Please find the same and kidly give me a suggestion 

 

Vishnu.gopi

 

0 Kudos
Visitor vish6353
Visitor
883 Views
Registered: ‎06-20-2018

Re: PCIE core is not detecting if I add DDR3 controller in the design

upto gen1 x4 it is detecting. if we go up further it is making issue.kindly tell some solution

0 Kudos
Moderator
Moderator
870 Views
Registered: ‎02-16-2010

Re: PCIE core is not detecting if I add DDR3 controller in the design

As a debug step, can you try to put DDR3 in reset and check the status of PCIe link?
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Visitor vish6353
Visitor
852 Views
Registered: ‎06-20-2018

Re: PCIE core is not detecting if I add DDR3 controller in the design

I tried that one also.still it is not detecting.

0 Kudos
Moderator
Moderator
846 Views
Registered: ‎02-16-2010

Re: PCIE core is not detecting if I add DDR3 controller in the design

Please refer to link training debug guide from AR#56616 (https://www.xilinx.com/support/answers/56616.html) and capture the debug signals from "Link Training Debug Signals" section.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Visitor vish6353
Visitor
837 Views
Registered: ‎06-20-2018

Re: PCIE core is not detecting if I add DDR3 controller in the design

I have roughly tried to capture this signals already.After Board power on LTSSM state came 16(L0 state).user lnk up status also was comming high. but whenever we try to boot the processor(using terminal access applications like putty)(processor will be initiating the PCIe),this state was gong to 2D(Timeout to detect), and user lnk status has gone low.clock lock status was coming high in both time

pcie pic1..jpg
0 Kudos
Visitor vish6353
Visitor
706 Views
Registered: ‎06-20-2018

Re: PCIE core is not detecting if I add DDR3 controller in the design

If i keep reset as '1', then the calib complete should come '0' right? but it is coming 1  agian

0 Kudos
Moderator
Moderator
690 Views
Registered: ‎02-16-2010

Re: PCIE core is not detecting if I add DDR3 controller in the design

Please check if the DDR3 controller reset is active-low.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Visitor vish6353
Visitor
681 Views
Registered: ‎06-20-2018

Re: PCIE core is not detecting if I add DDR3 controller in the design

yes,With reset and without reset there is no impact.but i have noticed some other things.

1.in every compailation the Rxlane detection behaviour is different.
one time LTSSM state was in 00 and user reset was high and Rx status all are in 0 state
i just added PL_RECEIVER_HOT_RESET in chipscope and compailed. now the LTSSM state entered to 2D and user reset changed to 0. and Rx status now changed to 4,5,7 (detection failure),some times in 1 lane , some times in 2 lanes or 4 lanes also.
I have attached the Chipscope screen shots along with this replay.kidly check it

what we can conclude from this tests? noise coupling is happening if i add DDR3 in the design? can you tell any solution?

singls_with_ddr_rst_1.png
singls_with_ddr_rst_2.png
singls_with_ddr_rst_3.png
singls_with_ddr_rst_4.png
0 Kudos
Visitor vish6353
Visitor
667 Views
Registered: ‎06-20-2018

Re: PCIE core is not detecting if I add DDR3 controller in the design

I am using Two DDR controllers.with one DDR it is getting detected, either of DDR3A or DDR3B(both I tried).

0 Kudos
Moderator
Moderator
610 Views
Registered: ‎02-16-2010

Re: PCIE core is not detecting if I add DDR3 controller in the design

The RXSTATUS shows that the received data is in error. Both RXDISPERR and RXNOTINTABLE errors are asserted. Also, Rx buffer underflow error.

Whether power supplies to MGT are shared with DDR. Can you probe the noise on the MGT supplies during the failure and passing condition? Monitor MGTAVCC, MGTAVTT.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Visitor vish6353
Visitor
208 Views
Registered: ‎06-20-2018

Re: PCIE core is not detecting if I add DDR3 controller in the design

Sorry for the delayed reply.we have changed the oscillator for the pcie coz it won't support gen2_x4. but still the issue is not resolved.we have tried the above mentioned possibility. but there is only 10mV variation between with DDR and without DDR, that is also with in the tolerence and no noise coupling  in these two conditions as well.there are differences in the MGTAVCC MGTAVTT dynamic current in the power report of these two deisgns. what could be the reason. i have attached the document with this reply. kindly look in to this and suggest any solution please.

0 Kudos
Moderator
Moderator
183 Views
Registered: ‎02-16-2010

Re: PCIE core is not detecting if I add DDR3 controller in the design

@vish6353

With MGTAVCC, MGTAVTTT - the total peak-to-peak noise as measured at the input pin of the FPGA should not exceed 10 mVpk-pk. Please check page 228 of ug482.

When you say the following, it seems the noise is more than the requirement mentioned in the GT user guide and can you check the reason for the increase in the noise on MGT supplies when DDR is added to the design?

there is only 10mV variation between with DDR and without DDR

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos