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Visitor srcampbell
Visitor
485 Views

PCIe DMA/Bridge and AXI Performance monitor BRAM reads returning Fs

I am trying to follow:

https://www.xilinx.com/video/technology/getting-the-best-performance-with-dma-for-pci-express.html

Using the driver from: https://www.xilinx.com/support/answers/65444.html

 

I am using a bittware, with an xcvu13P (xcvu13p-figd2104-2-e)

 

I set up my PCIe DMA/Bridge in DMA mode with a x16 8GT/s (Gen 3) PCIe Interface. I'm using all 3 bars (AXI Lite Master for the performance monitor, DMA (AXI_M) connected to the BRAMs, and the DMA BYPASS also connected to the BRAMs). I'm also using the AXI Lite Slave. I added the BYPASS since the DMA driver wasn't getting responses and I wanted to be able to write directly to the BRAMs. Now when I load the image, and read from BAR4 (Bypass), I get all Fs. I have added a system ila to both the dma AXI_M and to the bypass and I don't see any traffic when I issue writes. I also added an ila to look at the user_link signal and the reset signal. They are both high (reset is active low).

 

The BRAMs are connect through an AXI Smartconnect (2 Masters: M_AXI and BYPASS). The AXI performance monitor is connected via a axi interconnect (Master: AXI Lite Master, Slaves: AXI Lite Slave and Performance Monitor).

 

See images to see how the BARs, DMA, and addresses are configured.

 

root@positron1:~# busybox devmem 0x380040000000
0xFFFFFFFF

 

I read something here (https://forums.xilinx.com/t5/PCI-Express/Xilinx-Answer-65444-performance-test-failed/td-p/832761) about not using smart connect with PCIe IPs. Is this what is causing my issue?

 

I don't see any critical warnings or errors with synthesis.

dma_bridge_bars.png
address_editor.png
dma_bridge_dma.png
memory_mapped.png
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4 Replies
Xilinx Employee
Xilinx Employee
473 Views

Re: PCIe DMA/Bridge and AXI Performance monitor BRAM reads returning Fs

Can you put in an ILA on the PCIe core CQ/CC interface?  This will show if the PCIe request is even getting to the core.

 

 

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Visitor srcampbell
Visitor
455 Views

Re: PCIe DMA/Bridge and AXI Performance monitor BRAM reads returning Fs

How do you expose the PCIe core CQ/CC interface in the DMA/Bridge Subsystem for PCIe? Are these the signals that are exposed through enabling "Additional Tranceiver Control and Status Ports"?

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Visitor srcampbell
Visitor
390 Views

Re: PCIe DMA/Bridge and AXI Performance monitor BRAM reads returning Fs

Update: I made an image with just the dma and the bypass ports (no axi performance monitor, no AXI Lite Slave or AXI Lite Master). I also changed the PCIe to AXI to 0x0... This image works! I am able to dma and directly read/write to the brams.

Now without changing the address editor or the DMA/Bridge Subsystem for PCI Express configuration for the PCIe to DMA Interface or for the PCIe to DMA Bypass Interface, I added the AXI Lite Slave and Master back in. With this new image I again get Fs when trying to read from the bypass however the dma does still work.

 

Without the AXI Lite Master and Slave:
Region 0: Memory at f3800000 (32-bit, non-prefetchable) [size=64K] <- DMA
Region 2: Memory at f3400000 (64-bit, prefetchable) [size=4M] <- BYPASS

root@positron1:~# busybox devmem 0xf3400000
0x00000000
root@positron1:~# busybox devmem 0xf3800000
0x1FC00006
root@positron1:~# busybox devmem 0xf3400000 w 0xF
root@positron1:~# busybox devmem 0xf3400000
0x0000000F

 

With the AXI Lite Slave and Master:
Region 0: Memory at f3800000 (64-bit, prefetchable) [size=256K] <- AXI LITE
Region 2: Memory at f3900000 (32-bit, non-prefetchable) [size=64K] <- DMA
Region 4: Memory at f3400000 (64-bit, prefetchable) [size=4M] <- BYPASS

root@positron1:~# busybox devmem 0xf3800004
0x00000000
root@positron1:~# busybox devmem 0xf3400000
0xFFFFFFFF
root@positron1:~# busybox devmem 0xf3400000 w 0x000
root@positron1:~# busybox devmem 0xf3400000
0xFFFFFFFF

 

Now on the ILA on the image with the AXI Lite Master and Slave, I see that the address for the write is 0xC00000000 and without the AXI Lite Master/Slave it is 0x0 (like was specified).

 

Anyone know where this 0xC00000000 could have come from? Is there something about the BYPASS being on BAR 4 vs. BAR 2?

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Xilinx Employee
Xilinx Employee
280 Views

Re: PCIe DMA/Bridge and AXI Performance monitor BRAM reads returning Fs

Hi @srcampbell

 

Can you please post your XCI file?  Are you directly connecting BRAM behind the AXI Lite / Bypass interfaces or do you have an interconnect / smartconnect logic?

 

 

 

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