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Observer zangeneh
Observer
2,310 Views
Registered: ‎08-19-2016

Place:1201 - Component <s6_pcie_v2_4_i/pll_base_i/PLL_ADV> of type PLL is not placeable because it has locked loads placed in regions

I have a XC6SLX45T-3FGG484C device in my design that I would like to use the PIO module developed by Xilinx for Integrated
Endpoint Block PCI Express. The PCIe clock is 100 MHz. When I am trying to marry the PIO module with my logic design, I'm getting the mapping error as: 

 

ERROR:Place:1200 - Component <s6_pcie_v2_4_i/pll_base_i/PLL_ADV> LOC'd to site
<PLL_ADV_X0Y0> is not placeable for the following reason:
ERROR:Place:1201 - Component <s6_pcie_v2_4_i/pll_base_i/PLL_ADV> of type PLL is
not placeable because it has locked loads placed in regions: CLOCKREGION_X0Y6
CLOCKREGION_X0Y7 CLOCKREGION_X0Y7.
There is a restriction that the clock loads of a PLL must be in a
horizontally adjacent clock region to the PLL. It is recommended that a BUFG
be used for this clock signal so that the clock loads can be placed anywhere
on the device. If the clock driver or clock loads are locked or area grouped,
please ensure that they are constrained to horizontally adjacent clock
regions.

 

 

I am using the user_clk_out signal which is the 62.5 MHz output clock from the PLL module in the endpoint design. That clock is already buffered using BUFG. I very simply would like to use the 100 MHz PCIe clock differential signal for my design and for some reason the PLL module doesn't seem to be helpful. Any suggestions?

 

Regards,

Mo

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1 Reply
Observer zangeneh
Observer
2,309 Views
Registered: ‎08-19-2016

Re: Place:1201 - Component <s6_pcie_v2_4_i/pll_base_i/PLL_ADV> of type PLL is not placeable because it has locked loads placed in regions

Forgot to mention that I am using ISE 13.4 in this design.

 

Regards,

Mo

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