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Explorer
Explorer
629 Views
Registered: ‎06-15-2010

Programming file trouble for PCIe example project on AC701 with Artix7

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Hello!

Finding my way with Vivado, I've tried to generate PCIe example project in ISE for AC701 board with Artix7 device. It was rather straightforward, but I faced a trouble at programming file generation stage. I am getting error:

ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are
not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned.
This may cause I/O contention or incompatibility with the board power or
connectivity affecting performance, signal integrity or in extreme cases
cause damage to the device or the components to which it is connected. To
prevent this error, it is highly suggested to specify all pin locations and
I/O standards to avoid potential contention or conflicts and allow proper
bitstream creation. To demote this error to a warning and allow bitstream
creation with unspecified I/O location or standards, you may apply the
following bitgen switch: -g UnconstrainedPins:Allow

OF course, I've tried "-g UnconstrainedPins:Allow", after programming link does not get up, I see that as LED is off on the board and from Root Complex as well.

There is not that many ports in example design

module xilinx_pcie_2_1_ep_7x # (
  parameter PL_FAST_TRAIN     = "FALSE", // Simulation Speedup
  parameter PCIE_EXT_CLK      = "TRUE",  // Use External Clocking Module
  parameter C_DATA_WIDTH      = 64, // RX/TX interface data width
  parameter KEEP_WIDTH        = C_DATA_WIDTH / 8 // TSTRB width
) (
  output  [0:0]    pci_exp_txp,
  output  [0:0]    pci_exp_txn,
  input   [0:0]    pci_exp_rxp,
  input   [0:0]    pci_exp_rxn,

  output                                      led_0,
  output                                      led_1,
  output                                      led_2,
  output                                      led_3,

  input                                       sys_clk_p,
  input                                       sys_clk_n,
  input                                       sys_rst_n
);

So I edited contraints file to explicitly tell IOSTANDARD to all the pins as in attached file, it does not help. More over, if I check IOB properties, I see my constraints were not applied the way I expected:

IOB NameTypeDirectionIO StandardDiff TermDrive StrengthSlew RateReg (s)ResistorIOB Delay
led_0IOBOUTPUTLVCMOS18 12SLOW   
led_1IOBOUTPUTLVCMOS18 12SLOW   
led_2IOBOUTPUTLVCMOS18 12SLOW   
led_3IOBOUTPUTLVCMOS18 12SLOW   
pci_exp_rxn<0>IPADINPUT       
pci_exp_rxp<0>IPADINPUT       
pci_exp_txn<0>OPADOUTPUT       
pci_exp_txp<0>OPADOUTPUT       
sys_clk_nIPADINPUT       
sys_clk_pIPADINPUT       
sys_rst_nIOBINPUTLVCMOS18      

 

Please guide me in this trouble.

Thanks in advance.

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1 Solution

Accepted Solutions
Explorer
Explorer
26 Views
Registered: ‎06-15-2010

Re: Programming file trouble for PCIe example project on AC701 with Artix7

Jump to solution

Hi!

Just before I was able to run both Vivado & ISE example projects. With Vivado I changed nothing, just reconnected to root complex and it start working.

With ISE there seems to be some tools misbehaviour. Although I saw UCF in proper place of project hierarchy and correct association with implementation flow, when I edited UCF, the changes were not applied, so the UCF was not processed right way. I have cleaned project guts, removed and added UCF again, now it works fine again.

I remember I was adding Verilog sources and UCF in one run, probably that did its to me.

Anyway, the case is over, thank you for your support.

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2 Replies
Moderator
Moderator
587 Views
Registered: ‎01-15-2008

Re: Programming file trouble for PCIe example project on AC701 with Artix7

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could you try in vivado tool to generate an example design and test the same?

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Explorer
Explorer
27 Views
Registered: ‎06-15-2010

Re: Programming file trouble for PCIe example project on AC701 with Artix7

Jump to solution

Hi!

Just before I was able to run both Vivado & ISE example projects. With Vivado I changed nothing, just reconnected to root complex and it start working.

With ISE there seems to be some tools misbehaviour. Although I saw UCF in proper place of project hierarchy and correct association with implementation flow, when I edited UCF, the changes were not applied, so the UCF was not processed right way. I have cleaned project guts, removed and added UCF again, now it works fine again.

I remember I was adding Verilog sources and UCF in one run, probably that did its to me.

Anyway, the case is over, thank you for your support.

0 Kudos