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Registered: ‎06-25-2019

QDMA: How to manually configure master read/write burst size

Hi everyone,

I'm evaluating the QDMA performance between host memory and UltraRAM in FPGA. I enabled my simple QDMA design on the Alveo U250 which is very similar to QDMA example desgin provided by Xilinx.

My performance results show that Read throughput (FPGA -> Host) achieves around 100Gbps but Write throughput (Host -> FPGA) is around 80Gbps even if I changed parameter such as queue size and packet size (transfered data size).

I tried to identify the root cause of this bottleneck and found that AXI Burst Size is different between Read (FPGA -> Host) and Write (Host -> FPGA). Attached screenshots show the Burst Size differences monitored by ILA.


Read (FPGA -> Host)
ARLEN(m_axi_arlen[7:0]): 0x3F
ila_2.png

Write (Host -> FPGA)
AWLEN(m_axi_awlen[7:0]): 0x07
ila_1.png


I would like to know QDMA burst size is configurable or not and if it's configurable, how to change them. Please let me know if you have any information.


My environment.
- CPU: Intel(R) Core(TM) i7-5960X CPU @ 3.00GHz
- MEM: 32 GByte
- PCIe: Gen3 x16
- FPGA: Alveo U250
- QDMA IP: 2018.3_AR72013
- URAM: 4 MByte
- Vivado: 2018.3
block_diagram.png

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