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multi access to RAM using DMA/Bridge for pcie and others cores

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Visitor fab
Visitor
Posts: 8
Registered: ‎04-09-2018

multi access to RAM using DMA/Bridge for pcie and others cores

Hi everybody,

I woud ask you a question simple in its construction but huge in its implication. I want build a connection between a linux machine and a kc705 using the PCI express bus. I can use the design DMA/Bridge + MIG to access the RAM and tet the PCI Express. Now I want to use the pci as bus to download data from the transceivers to the linux machine, using the RM as bufffer for the time synchronization. Can I access on RAM from "DMA/Bridge for PCI express" and from another core (example: Microblaze, axi traffic generator,..), when the DMA/Bridge is in Endpoint mode? Thanks for your help and your attention.

Visitor fab
Visitor
Posts: 8
Registered: ‎04-09-2018

Re: multi access to RAM using DMA/Bridge for pcie and others cores

*to build

*test

*RAM

Hi everybody,

to be more precise, I am using Vivado 2016.4, the bus is a PCI Express Gen 2 x8, I have the driver for the xdma (the driver made by Xilinx), I have started this task 1 and an half month ago, starting to study the PCI Express and the core provided by Vivado. What I have understand until now, is that what I want to do (multi-access on the kc705 RAM from the DMA/Bridge for PCI Express and from another core) I can do it only using a PCI Express core in Root Complex mode or in Legacy Endpoint mode. I am trying to understand if  the DMA/Bridge core can : generate an interrupt usable by the Microblaze so to let it (the Microblaze) to manage the access on the kc705 RAM and to move the access on RAM from the Microblaze to the DMA/Bridge and viceversa, or manage itself the access on the kc705 RAM managing the interrupt from other cores; all this in Endpoint mode, because the DMA/Bridge on the kc705 has only this mode to work, and because , as i understand, I can't create a connection from 2 Root Complex PCI Express. Thanks for your help and your attention.

Xilinx Employee
Posts: 215
Registered: ‎08-06-2008

Re: multi access to RAM using DMA/Bridge for pcie and others cores

Hi,

 

Could you please post a block diagram of your system? It would be easier to understand.

Regarding the interrupts, you can generate interrupt in your endpoint to be processed by your root complex.

 

Thanks.

Visitor fab
Visitor
Posts: 8
Registered: ‎04-09-2018

Re: multi access to RAM using DMA/Bridge for pcie and others cores

Hello deepeshm,

thanks for your answer. This is the scheme of my "idea" of how to make the design. I would know if there is an interrupt signal (or if I can generate it)  from the DMA/Bridge core for PCIe processable by the microblaze as interrupt, so to manage the access to my board's RAM and decide if the Microblaze or the DMA/Bridge for PCIe has to access it. Thanks for your help.

fab

Visitor fab
Visitor
Posts: 8
Registered: ‎04-09-2018

Re: multi access to RAM using DMA/Bridge for pcie and others cores

Hi everybody,

I will try one lat time to give more info to find  an answer to my question. When I talk about "interrupts", I am not talking about the interrupts of the PCI Express protocol (Legacy or MSI). That type of interrupts I know how to use it. When I use the word "interrupts", I am talking about the interrupts necessary to access the RAM of my board, which will be the endpoint of my project. To make an example, in the Product Guide of the AXI Memory Mapped to PCI Express, there is a signal called interrupt_out which:

"The interrupt_out pin signals interrupts to  devices attached to the memory mapped AXI4 side of the bridge." (PG055, pg 56). This signal let me to manage the "interrupts" inside my AXI4 design. There is a similar output signal for the DMA/Bridge for PCI Express IP? Thanks for your help and your attention.

fab

 

Xilinx Employee
Posts: 215
Registered: ‎08-06-2008

Re: multi access to RAM using DMA/Bridge for pcie and others cores

Hi,

Apologies. I missed your reply. No we don't have interrupt_out type signal in the DMA mode. If you are looking to check if engine started or finished, you could use c2h_sts and h2c_sts ports that will give user status of the engine in real time. You could write a logic to convert it into interrupt registers.

Thanks