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Visitor
Visitor
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Registered: ‎08-09-2020

2 Slots PCIe UltraScale+ MPSOC

I am working on a carrier card design for the UltraZed-EV SOM and I need to create two Gen3 mini pci-e slots on it.  Since mini pci-e is always a single lane, my thought is to simply make a 2-lane root complex bridge and run a lane to each slot.  But I have no idea if link negotiation, etc. would work.  I'm not sure if this is a legitimate methodology to simply split up the lanes, or if I would have to get fancier using something like a 2x2 crossbar switch or a full PCIe switch. 

Generally speaking, the reference design information that is available has been quite useful in working through this, and has good info about a single PCIe port, but I'm unable to locate any set of schematics or information that detail more than one slot that I could use as a reference.

Any input would be appreciated.

Thanks,

Keith   

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-26-2012

I'm not sure if I understand the question correctly, but there is no ability for MPSoC PCIe RP to split x2 lanes into x1 two links. It is needed to connect to the two endpoints via a PCIe switch.

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