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Observer
Observer
11,488 Views
Registered: ‎12-16-2014

AXI Bridge for PCIe hangs

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I'm using the AXI MM to PCIe Bridge IP (v2.5) as PCIe endpoint in an IP Integrator design with Vivado v2014.4 running on a ZC706 installed into a Linux workstation running 64-bit Ubuntu Linux 14.04.  The design enumerates and shows up with the right link speed and lane width in the system according to lspci.

My immediate goal is to access Linux workstation RAM from the Zynq over PCIe.  The problem I'm seeing is that when I initiate a read (or write) from the Zynq to system RAM through the Bridge, the AXI cycle to the Bridge seems to hang and lock up the Zynq.

The PCIe/AXI bridge connections are:
* Bridge M_AXI <-> AXI4 Interconnect 0 <-> PS7 S_AXI_GP0
* Bridge S_AXI <-> AXI4 Interconnect 1 <-> PS7 M_AXI_GP0
* Bridge S_AXI_CTL <-> AXI4 Interconnect 2 <-> PS7 M_AXI_GP1

I don't need three interconnects, but intentionally isolated them as a debug step trying to identify the problem.

I have one 64-bit AXI BAR enabled and program its address translation registers (AXIBAR2PCIEBAR_0U, AXIBAR2PCIEBAR_0L) with the 64-bit address returned by my Linux host app memory allocation routine.

I've used chipscope (oops...I mean Vivado Debug) to observe the AXI transaction on the Bridge S_AXI port.  It shows the AXI transaction beginning with the proper address, ARVALID asserting, but ARREADY never asserts and the transaction just hangs.

Lastly, note that I am able to go the other way through the Bridge, i.e. I can access Zynq resources from the Linux workstation.

Any ideas?

Thanks,
-K

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Scholar
Scholar
19,817 Views
Registered: ‎02-03-2010

Hi

 

Can you check bus master enable bit in the config space of the PCIe core is set.

I think the arready is assetted oly when core is cpable of sending any upstream packets.

With out he BME bit in command register of config space , the core will not be able to do it.

 

 

regards,

KR

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5 Replies
Scholar
Scholar
19,818 Views
Registered: ‎02-03-2010

Hi

 

Can you check bus master enable bit in the config space of the PCIe core is set.

I think the arready is assetted oly when core is cpable of sending any upstream packets.

With out he BME bit in command register of config space , the core will not be able to do it.

 

 

regards,

KR

--------------------------------------------------​--------------------------------------------
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Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

View solution in original post

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Observer
Observer
11,458 Views
Registered: ‎12-16-2014

Thank you, KR.  That was the problem.

 

-K

 

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Newbie
Newbie
10,431 Views
Registered: ‎05-12-2015

hi  KR:

I have the same problem, as you say, the bus master enable(BME) bit in the config space of the PCIe core should be set. But in the AXI birdge for PCIe IP core config list I can't fine the BME option, and in its datasheet Pg055 said that

"For 7 series devices, this area is read-only when configured as an
Endpoint. Writes are permitted for some registers when a 7 series device is configured as a
Root Port.
"

So how can I enable the BEM bit? what should I do ? looking forward your reply. thanks~!

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Newbie
Newbie
10,429 Views
Registered: ‎05-12-2015
hi logicaledge ,
I have the same problem , the bus master enable(BME) bit in the config space of the PCIe core should be set. But in the AXI birdge for PCIe IP core config list I can't fine the BME option, and in its datasheet Pg055 said that
"For 7 series devices, this area is read-only when configured as an
Endpoint. Writes are permitted for some registers when a 7 series device is configured as a
Root Port. "
So how can I enable the BEM bit? what should I do ? looking forward your reply. thanks~!
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Mentor
Mentor
8,528 Views
Registered: ‎08-24-2011
That should be done with pci_set_master in the Linux driver at PC side.
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