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hanyueliuxing
Visitor
Visitor
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Registered: ‎05-23-2018

AXI Bridge for PCIe problem

I'm using the AXI MM to PCIe Bridge IP (v2.8) as PCIe endpoint in an IP Integrator design with Vivado 2016.1 running on a K7 325T board installed into a PC running 64-bit win7. 

The design include AXI_LITE module  , AXI master module and AXI slave module in K7 FPGA. The AXIBAR2PCIEBAR_0L ( offset 0X20C,32- bit address space ) is configured through AXI_LITE module. Data can be write to a user space allocated by the driver through the AXI master module some time and  failed sometime. But reading the user space always fail and no data is received. The waveform list below. 

The process of AXI master writing is correct as shown in the figure.The process of AXI master reading is failed as no rvalid signal from the bridge core. 

I need help.

Thanks

AXI master write.png
AXI master read.png
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venkata
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Moderator
576 Views
Registered: ‎02-16-2010

@hanyueliuxing

Is it possible for you to migrate to the latest Vivado release 2018.2?

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