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Registered: ‎04-12-2012

AXI Bridge vs DMA/Bridge Subsystem for PCI Express


An Ultrascale FPGA I'm working on has a hardened PCIe endpoint that connects to an Intel CPU with 8 PCIe lanes.
I want to avoid custom management of the TLP layer.
As far as I understand - Xilinx provides 2 free componets that can do this:

• AXI Bridge for PCI Express Gen3
• DMA/Bridge Subsystem for PCI Express (in AXI Bridge mode)

In the past I used the DMA/Bridge for this purpose and it worked well. I have no experience with the AXI bridge though...and I'm wondering how they compare.

This is what I found in PG194:
The Master Bridge in AXI Bridge for PCIe Gen3 core can
support up to 8 active PCIe MemWr request TLPs. The Master Bridge in DMA/Bridge Subsystem for PCIe in AXI Bridge mode core can support up to 32 active PCIe MemWr request TLPs.

To users that worked with both:
What else can the DMA/Bridge do that the AXI Bridge can't ?

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