AXI-Memory Map & AXI Streaming User Interface for PCIe DMA Subsystem

[nsy_0415@hotmail.com]

According to DMA for PCIe subsystem description below,
https://www.xilinx.com/products/intellectual-property/pcie-dma.html

1) AXI-Streaming is meant for RTL-based design

2) AXI-Memory Map is meant for Full AXI-based design

Does this mean AXI Memory Map user interface is not suitable to used in RTL based design? Any other consideration other than the reason is stated in above 2 bullet points?

In other word, which user interface is most common used to build a PCIe sub-system in FPGA world?

[cllin_nctu]

In my option, PCIe integrated block (AXI-stream) handles PHY and Link layer packet, and user needs to handle most of transaction layer, such as MemRd/Wr, messages. For AXI bridge subsystem (AXI-memory Map), it handles all PCIe transaction and transfer MemRd/Wr to AXI.