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Observer
Observer
374 Views
Registered: ‎12-08-2019

AXI Memory Mapped to PCI Express IP:When a part of Lane is disconnected

Hello,
 
・ Vivado 2018.3
・ AXI Memory Mapped to PCI Express IP: EP, Gen1, x2
・ Simurator: Xcelium 19.11-a001
When IP is generated by x2 and connected to RP by x2, what will happen to EP under the following conditions?
 
1. When RP starts Link Traning on x1
2. When pci_exp_txp / n [1] and pci_exp_rxp / n [1] are disconnected
3. When pci_exp_txp / n [0] and pci_exp_rxp / n [0] are disconnected
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Observer
Observer
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Registered: ‎12-08-2019

If you are a Xilinx Employee, please comment.
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Xilinx Employee
Xilinx Employee
299 Views
Registered: ‎08-02-2007

1 X1 can be built 

2 link up with x1 on gt0

3 if lane reversal is enabled, link up to x1 on gen1, if not , link is down

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Observer
Observer
290 Views
Registered: ‎12-08-2019

Thank you for your answer.

Do conditions 2 and 3 automatically link-up again?
In the simulation, how long can pci_exp_txp / n [1] be 0-clamped to reproduce?

In the simulation, I can confirm the link down when pci_exp_txp / n [1: 0] is clamped to 0 about 100us.

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Observer
Observer
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Registered: ‎12-08-2019

If you are a Xilinx Employee, please comment.
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