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Registered: ‎01-24-2020

AXI Memory Mapped to PCIe Error: i_true_dual_port_blk_mem_gen is not declared

Currently using:
Vivado version: 2019.2
OS: Windows 10
Target board: ZC706 (ZYNQ 7045)

I am making some tests to understand the usage of the Axi Memory Mapped to PCIe IP, but when I try to simulate my project I always run into the error message:

 

Starting static elaboration
Pass Through NonSizing Optimizer

####################################
#### MAIN ERROR HERE 
####################################

ERROR: [VRFC 10-2989] 'i_true_dual_port_blk_mem_gen' is not declared
ERROR: [VRFC 10-2989] 'i_true_dual_port_blk_mem_gen' is not declared
ERROR: [VRFC 10-2989] 'i_true_dual_port_blk_mem_gen' is not declared

WARNING: [VRFC 10-4969] module 'axi_pcie_v2_9_2_pcie_7x_v2_0_2_gt_top' is instantiated multiple times from VHDL or from both Verilog and VHDL, elaboration result may be incorrect [/wrk/2019.2/continuous/2019_11_06_2708876/packages/customer/vivado/data/ip/xilinx/axi_pcie_v2_9/hdl/axi_pcie_v2_9_rfs.v:20313]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'wea' [/wrk/2019.2/continuous/2019_11_06_2708876/packages/customer/vivado/data/ip/xilinx/axi_traffic_gen_v3_0/hdl/axi_traffic_gen_v3_0_rfs.v:13456]
WARNING: ...

Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
...

Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav

****** Webtalk v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:40:23 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

...

INFO: [USF-XSim-69] 'elaborate' step finished in '437' seconds
INFO: [USF-XSim-99] Step results log file:'...'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or ... file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:31 ; elapsed = 00:07:41 . Memory (MB): peak = 1009.008 ; gain = 4.699
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

 

 

I do not explicitly declare the variable pointed out to be causing the error in my simulation top-level file (testbench.sv) nor in my block diagram and therefore I do not understand how it is causing an error. I would like to ask you to help me to identify what is causing this error and how to solve it.

My testbench file is: 

 

`timescale 1ns / 100ps

module testbench;

bit clk;
bit reset_n;

bit done;

logic [31:0] gpio_in;
wire [31:0] gpio_out;

design_1_wrapper design_tester(
    .clk_100MHz(clk),
    .reset_n(reset_n),
    .done_0(done),
    .GPIO2_0_tri_i(gpio_in),
    .GPIO_0_tri_o(gpio_out)
);

always 
begin
    #5 
    clk <= 1; 
    #5 
    clk <= 0; 
end

initial
    begin
        reset_n  = 0;
        #100
        
        reset_n = 1;
        gpio_in <= 32'hF0F0;
    end

endmodule

 

It basically imports an HDL file auto-generated from a Block Diagram and defines an initialization procedure through the reset. In this block diagram (attached file  bf_with_pcie_mem_mapped.pdf), I am using as IPs:

  • AXI Memory Mapped to PCIe
  • AXI Interconnect
  • AXI Traffic Generator
  • Processor System Reset
  • AXI GPIO

I have made the same design removing the AXI Memory Mapped to PCIe IP's and connecting the AXI Interconnects directly to one another, keeping all other IP's, and, in this case, I do not have the error. The block diagram, in this case, is depicted in the file bd_without_pcie.pdf.

I am not uploading my entire projects here just because the project folders are larger than the attachment limit.
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3 Replies
512 Views
Registered: ‎01-24-2020

When simulating this testbench with ModelSim (instead of Vivado Simulator) I no longer have the error.

For doing so, configure Project Settings >> Simulation Settings >> Target Simulator to use ModelSim Simulator, which is a third party simulation tool. You may also need to install and configure the corresponding software before configuring before trying to use it from Vivado.

It would be nice if someone could explain to me why changing the simulator solved the issue, or what was its origin in the first place.

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Visitor
Visitor
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Registered: ‎05-20-2020

I have the same error. I don't have a Modelsim, so i use a solution for the Vivado Simulator.

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Observer
Observer
287 Views
Registered: ‎05-21-2018

Same error, it exists in Vivado 2019.2 and 2020.1

For me, in file lib_bmg_v1_0_rfs.vhd it is the declaration name in caps I_TRUE_DUAL_PORT_BLK_MEM_GEN for the block memory generator.  I can simulate using a verilog file to connect the modules.  If I try to use a Block Design in IP Integrator I get the error and simulation does not run

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