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550 Views
Registered: ‎10-01-2020

AXI Memory mapped to PCIe - WRAP burst / Cacheable transactions

Hello Everyone,

 

In the IP core datasheet it is mentioned that only INCR burst type access is supported.

This is a blocker for my design. I am wondering if a workaround or patch is available from Xilinx to support WRAP burst transactions.

Also curious to know if the memory supports Cacheable transactions.



 

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2 Replies
543 Views
Registered: ‎10-01-2020

Please let me know if an alternative to this bridge is available which supports WRAP burst and Cacheable memory transactions.

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garethc
Moderator
Moderator
417 Views
Registered: ‎06-29-2011

HI @Arpitrathi31260 

Can you take a look at our PCIe and CPM board - Useful Resources sticky post from the link below.

https://forums.xilinx.com/t5/PCIe-and-CPM/PCIE-and-CPM-Useful-Resources/td-p/1079558

This details all our PCIe IPs including our bridge IPs and you can review them but to my knowledge we only support INCR burst type.

Thanks,

Gareth


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