10-01-2020 10:06 AM
In the IP core datasheet it is mentioned that only INCR burst type access is supported.
This is a blocker for my design. I am wondering if a workaround or patch is available from Xilinx to support WRAP burst transactions.
Also curious to know if the memory supports Cacheable transactions.
10-14-2020 01:10 AM
Can you take a look at our PCIe and CPM board - Useful Resources sticky post from the link below.
This details all our PCIe IPs including our bridge IPs and you can review them but to my knowledge we only support INCR burst type.