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Visitor
Visitor
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Registered: ‎11-05-2018

Accessing PCIe Endpoint BAR Space From Zynq Side

Hi,

I am using zynq xc7z045 and want to access pcie endpoint's bar space from zynq with AXI Memory Mapped To PCI Express core.

I configured zynq as root complex and run xaxipcie_rc_enumerate_example as succesfully.

My  PCIE:BARS Configuration:

PCI-BARS.png

My AXI:BARS Configuration:

AXI-BARS.png

 

My Address Editor:

Address Editor.png

 

End Point's BAR space size is 128 kb and I configured BAR0 with 0x61000000 via XAxiPcie_WriteRemoteConfigSpace function and read same value.

I try to read offset 0x10 with following commands:

 

 

 

UINTPTR bar0addr=0x61000000;
uint32_t readData;
uint32_t* some_reg=(uint32_t*)(bar0addr+0x10);
readData=*some_reg;

 

 

 

But program crashes in "readData=*some_reg" line.

Could you help about this problem.

Thanks

 

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Xilinx Employee
Xilinx Employee
30 Views
Registered: ‎08-02-2007

have you checked the bus master bit yet?

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