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btonner
Observer
Observer
5,552 Views
Registered: ‎05-03-2011

Approach to XAPP1052 addition of memory

Hello

 

I have a number of short question

 

I am trying to add a memory module to the xapp1052 endpoint example and am wondering if I have taken the wrong approach to this problem as others do not seem to be having the same level of difficulty. I got the test app working but now I need to store/send the data.

 

-First off, there seems to be no test bench. I am new to xilinx tools and verilog (more used to other guys) so perhaps I ave missed something? I read somewere that I might request one from xilinx, is this the case? Or are there some floating around somewere.

 

-I am modifying the TX and RX modules to read/write the data to a fifo as seemed appropriote to me but since I am having a lot of timing issues some indication that this is not a terrible approach would be helpful. I know coregen can generate additional brams and its hard to imagine that there is not a better way to go about this.

 

-Does anyone use chipscope? I am wondering if there are perhaps some limitations or bugs that are causing it to not trigger properly on some of my signals.

 

Thats all, thanks in advance.

 

 

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luisb
Xilinx Employee
Xilinx Employee
5,533 Views
Registered: ‎04-06-2010

You are correct that XAPP1052 does not come with a testbench.  However, you can still use the PIO example design testbench and use the test that I'm attaching.  I haven't used this one on my own, so use at your own risk.

 

I'm not sure which tx and rx modules you're talking about, so I can't comment.

 

I have used ChipScope a lot and I've never had the problem that you're running into.  Which flow are you using?  Inserter or Coregen Flow?

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btonner
Observer
Observer
5,501 Views
Registered: ‎05-03-2011

Many thanks Luis.

 

I have finally gotten around to setting up the simulation now that I am ready to start integrating parts of my project. I have gotten ISIM up and running with the "Board.v" test bench. 

 

The only difference from out of the box coregen specifications is that the DMA design files are included

 

I am getting these errors when I launch isim:

 

10s of warnings such as: 

WARNING: For instance gtx_v6_i/\GTXD[6].GTX /, width 1 of formal port PERFCLKRX is not equal to width 32 of actual constant.

I am not sure if these are trivial, or signifigant

 

and this repeating error:

 

[ 0] : System Reset Asserted...

Finished circuit initialization process.

DRC Error : Reset is unsuccessful at time 107906. RST must be held high for at least three RDCLK clock cycles, and RDEN must be low for four clock cycles before RST becomes active high, and RDEN remains low during this reset cycle.

DRC Error : Reset is unsuccessful at time 107906. RST must be held high for at least three WRCLK clock cycles, and WREN must be low for four clock cycles before RST becomes active high, and WREN remains low during this reset cycle

 

Can these by ignored or they indicative of a problem with the way I am running the simulation? 

 

I should also note that the simulation is running very slowely and taking up 3GB of memory. Is this typical for this project?

 

Thanks

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luisb
Xilinx Employee
Xilinx Employee
5,469 Views
Registered: ‎04-06-2010

If you see these messages are far before the deassertion of the reset, then you're most likely ok ignoring them.

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btonner
Observer
Observer
5,441 Views
Registered: ‎05-03-2011

I am admittably mostly concerned about the resourses being used by the simulation, is this typical, and need I - as I sim directed - be configuring the cores for structural simulation?

 

Thanks

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