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Visitor lkantoski
Visitor
591 Views
Registered: ‎12-12-2016

Atrix 7 - Integrated Block for PCI Express v3.3 Timing Violations

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I am trying to build project using the PCI Express IP core and have been seeing various setup time violation related to signals within ip core.

Here is a couple of the signals failing timing:

From:

RTD_PCIe_Interface_i/U0/inst/pcie_top_i/axi_basic_top_i/rx_inst/rx_null_gen_inst/reg_pkt_len_counter_reg[4]/C

To:

RTD_PCIe_Interface_i/U0/inst/pcie_top_i/axi_basic_top_i/rx_inst/rx_pipeline_inst/reg_tlast_reg/D

 

From:

RTD_PCIe_Interface_i/U0/inst/pcie_top_i/axi_basic_top_i/rx_inst/rx_null_gen_inst/reg_pkt_len_counter_reg[4]/C

To:

RTD_PCIe_Interface_i/U0/inst/pcie_top_i/axi_basic_top_i/rx_inst/rx_pipeline_inst/trn_rdst_rdy_xhdl4_reg/D

 

I have seen these off and on between Vivado 2017.1 through 2017.4.

 

I also see similar violations with the example IP design. I have attached the example IP design that sees the violations. The project was generated in 2017.4.

 

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Moderator
Moderator
702 Views
Registered: ‎02-16-2010

Re: Atrix 7 - Integrated Block for PCI Express v3.3 Timing Violations

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I could reproduce the timing violations using your project. I find that the same project is closing timing with the next vivado release (2018.1).
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Moderator
Moderator
703 Views
Registered: ‎02-16-2010

Re: Atrix 7 - Integrated Block for PCI Express v3.3 Timing Violations

Jump to solution
I could reproduce the timing violations using your project. I find that the same project is closing timing with the next vivado release (2018.1).
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

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