04-11-2012 07:08 AM
for the recent project, I have to analyse a system, which uses the PCI-Express Axi Bridge (axi_pcie 1.02.a). Due to my simulation results (see attachment), I saw that I lose nearly half of the performance of PCIe throughput with 4 lanes.
I discovered in the vhd-file axi_slave_write.vhd (axi_pcie_mm_s_v1_02_a) that only one burst is executed at a time till it is sent to the PCIe hardmarco. Not till then, the next AXI burst can be executed.
Is there a special reason, why the transmission from AXI Memory Mapped to FIFO and FIFO to AXI-Stream is not pipelined?
04-12-2012 06:25 PM
Thanks for your reply,
I'll forward this info to my colleagues.
When can we expect the release of 14.1? Couple of months, half a year?
This could be a critical information how to proceed with our project.