cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
7,491 Views
Registered: ‎09-20-2011

Axi Bridge: Throughput reduction

Hello,

 

for the recent project, I have to analyse a system, which uses the PCI-Express Axi Bridge (axi_pcie 1.02.a). Due to my simulation results (see attachment), I saw that I lose nearly half of the performance of PCIe throughput with 4 lanes.

 

I discovered in the vhd-file axi_slave_write.vhd (axi_pcie_mm_s_v1_02_a) that only one burst is executed at a time till it is sent to the PCIe hardmarco. Not till then, the next AXI burst can be executed.

 

Is there a special reason, why the transmission from AXI Memory Mapped to FIFO and FIFO to AXI-Stream is not pipelined?

 

 

-----------------------------------------------------------------------------------------
It's always good practice giving feedback, when description/solution/recommendation have been helpful!
bottleneck_axibridge.png
0 Kudos
3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
7,481 Views
Registered: ‎04-06-2010

This is a known restriction in v1.02a
This is fixed in v1.03a, scheduled to come out in 14.1

Hope this helps.
0 Kudos
Highlighted
Observer
Observer
7,469 Views
Registered: ‎09-20-2011

Thanks for your reply,

 

I'll forward this info to my colleagues.

 

When can we expect the release of 14.1? Couple of months, half a year?

This could be a critical information how to proceed with our project.

-----------------------------------------------------------------------------------------
It's always good practice giving feedback, when description/solution/recommendation have been helpful!
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
7,457 Views
Registered: ‎06-01-2011

Hi,

 

14.1 is planned to be released in about a month (May timeline).

 

Thanks,

Chris

0 Kudos