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Adventurer
Adventurer
12,654 Views
Registered: ‎11-04-2010

Axi Memory Mapped to PCI Express S_AXI and S_AXI_CTL differences

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Hello,

 

I am currently working on a design where I make use of an AXI Memory Mapped to PCI Express core.

I am quite confused, though, regarding the S_AXI and S_AXI_CTL interfaces.

Which one should I use in order to transfer data from my board to a root complex through PCI-Express?

Do I have to use both of them?

Which are their differences?

Thank you in advance!

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Xilinx Employee
Xilinx Employee
22,017 Views
Registered: ‎12-10-2013

Re: Axi Memory Mapped to PCI Express S_AXI and S_AXI_CTL differences

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Hi,

 

For the AXI MM PCIe core, there are two AXI bridges contained in the core.   They each serve a different function, so each can be used at your discretion.  

 

(Remember in PCIe there are 2 ways to "send data to the Root Port"  -- (a) The RP requests the data, and the EP responds with a Completion w/ Data TLP   or  (b) The EP initiates a data transfer through a request -- generally MemWr TLP)

 

For an endpoint, on the AXI side of the core:

 

-  m_axi_ signals are outputs from the core are used to receive in requests from the upstream device.  On the PCIe RX side, these would be CfgRd, CfgWr, MemRd, MemWr, and so on.  

- m_axi_ signals that are inputs into the core to respond with the Completion or Completion w/ data to the requests from the upstream device.

 

- s_axi signals that are inputs to the core (on the slave bridge side) are for your endpoint device to send request upstream to the Root Port.  This requires that the root port will grant the EP the right to bus master.   A lot of users who only wish to respond to upstream requests do not use this interface.

- s_axi singals that are output from the core are specifically for the receipt of the completions to the requests going out on the s_axi interface.  Again, if you are only going to be responding to the root port, then you don't need this connected.

 

The CTL signals / bus are specifically used for access to the core for configuration and control.  These signals do not cause anything externally to the core to happen, but can be used for setting internal R/W registers, and (for example) reading your IP core's configuration space after enumeration. 

 

This image does not include the ctl signals, but does show the data directionality, naming, and memory addressing for both sides of the core. 

 

Conceptual Drawing

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9 Replies
Xilinx Employee
Xilinx Employee
22,018 Views
Registered: ‎12-10-2013

Re: Axi Memory Mapped to PCI Express S_AXI and S_AXI_CTL differences

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Hi,

 

For the AXI MM PCIe core, there are two AXI bridges contained in the core.   They each serve a different function, so each can be used at your discretion.  

 

(Remember in PCIe there are 2 ways to "send data to the Root Port"  -- (a) The RP requests the data, and the EP responds with a Completion w/ Data TLP   or  (b) The EP initiates a data transfer through a request -- generally MemWr TLP)

 

For an endpoint, on the AXI side of the core:

 

-  m_axi_ signals are outputs from the core are used to receive in requests from the upstream device.  On the PCIe RX side, these would be CfgRd, CfgWr, MemRd, MemWr, and so on.  

- m_axi_ signals that are inputs into the core to respond with the Completion or Completion w/ data to the requests from the upstream device.

 

- s_axi signals that are inputs to the core (on the slave bridge side) are for your endpoint device to send request upstream to the Root Port.  This requires that the root port will grant the EP the right to bus master.   A lot of users who only wish to respond to upstream requests do not use this interface.

- s_axi singals that are output from the core are specifically for the receipt of the completions to the requests going out on the s_axi interface.  Again, if you are only going to be responding to the root port, then you don't need this connected.

 

The CTL signals / bus are specifically used for access to the core for configuration and control.  These signals do not cause anything externally to the core to happen, but can be used for setting internal R/W registers, and (for example) reading your IP core's configuration space after enumeration. 

 

This image does not include the ctl signals, but does show the data directionality, naming, and memory addressing for both sides of the core. 

 

Conceptual Drawing

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Adventurer
Adventurer
12,635 Views
Registered: ‎11-04-2010

Re: Axi Memory Mapped to PCI Express S_AXI and S_AXI_CTL differences

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Thank you very much for your reply!
You relly helped me to better understand the AXI-PCIe Bridge core.
I will certainly make use of all the information you provided to me!
Thank you again!
Visitor richchen
Visitor
12,584 Views
Registered: ‎07-23-2014

Re: Axi Memory Mapped to PCI Express S_AXI and S_AXI_CTL differences

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For the s_axi interface, does this IP support 64-bit addressing of s_axi_araddr and s_axi_awaddr? I use Vivado 2014.2 for generating the AXI Memory Mapped To PCI Express (2.4) ip. The GUI only has 32-bit but no 64-bit s_axi address width option. Our logic need to send upstream request to a Root Port runs with 64-bit Linux. Although C_AXIBAR_NUM supports up to 6 address translation from 32-bit AXI address to 64-bit PCI address, it does not fit our needs as our requirement is to be able to access full 64-bit Host Memory space dynamically from the AXI bus. Any suggestion? Thanks!

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Visitor kamlendra17
Visitor
5,104 Views
Registered: ‎07-22-2016

Re: Axi Memory Mapped to PCI Express S_AXI and S_AXI_CTL differences

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Hi,
Problem statement
: 1.We have a daughter card having (FPGA and ADC) which will sit over mother card 2.Daughter card will sit over XMC connector interacting to processor over PCIe express Approach: I am trying to use AXI-PCIe bridge IP to enable this interfacing, so I pump adc data in AXI format and it will automatically get converted to tlp packets for PCIe interface ---------------For the same purpose I am Implementing AXI Master to interact with AXI slave in AXI-PCIe bridge ip -------------------------> I have implemented state machine for write ------------------------->Put address and taken care of other control signals from master side --------------------------------------But not getting any response from slave (AXI-Pcie bridge) like AWREADY to enable further communication.
Issues: Do I need to take care of any other things on slave side of (AXI-PCIe) bridge, because I am simulating stand alone AXI-PCIe bridge?? Is there any particular way of simulating this ip?? Have attached my VHDL implementation and behavioral simulation snapshot. Will highly appreciate any leads in this area or you could link us to some good links. Thanks, Kamlendra Chandra Central Research lab Bangalore
snapshot.PNG
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Visitor ewickram1
Visitor
3,256 Views
Registered: ‎02-09-2018

Re: Axi Memory Mapped to PCI Express S_AXI and S_AXI_CTL differences

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hi,

I am having the same issue. i do not see the 64 bit address generated on the pcie side. I have  set axitopcie bar registers similar to ug194 page 60. But, i do not see the correct 64 bit address generated to the pcie. upper 32 bits are always zero.

Any other settings need to be done?

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Xilinx Employee
Xilinx Employee
3,086 Views
Registered: ‎12-10-2013

Re: Axi Memory Mapped to PCI Express S_AXI and S_AXI_CTL differences

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Hi @richchen,

 

The AXI Memory Mapped to PCI Express Gen 2 core, specifically, only supports 32-bit addressing on the AXI side of the core. 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Re: Axi Memory Mapped to PCI Express S_AXI and S_AXI_CTL differences

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Hi @ewickram1

 

Can you please confirm that you are using the AXI Bridge for PCIe Gen3 IP, and not the AXI Memory Mapped Bridge for Gen2? 

 

If you can provide your XCI file on your generated IP, we can take a look.  Please make sure you are trying this in the most recent version of the IP.

 

Sincerely,

Beth

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Visitor ewickram1
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Registered: ‎02-09-2018

Re: Axi Memory Mapped to PCI Express S_AXI and S_AXI_CTL differences

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I am using xdma version 4.0.

here is the .xci file.

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Xilinx Employee
Xilinx Employee
2,710 Views
Registered: ‎12-10-2013

Re: Axi Memory Mapped to PCI Express S_AXI and S_AXI_CTL differences

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Hi @ewickram1

 

This is a different core and is going to have some significant differences than the solution posted.  Can you please start a new thread on this topic so that we make sure it gets a good answer?

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