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Participant sreevenkjan
Participant
822 Views
Registered: ‎03-12-2018

Bus Master Enable bit of Endpoint from Rootcomplex

Hi experts,

 

I have a axi bridge PCIe IP as root complex with an address 0x10000000 where I can read the RC PCI config space.

 

How can I set EP bus master enable from RC? All I can do right now is read the RC config space using the address 0x10000000.

 

Thanks,

SV

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Participant sreevenkjan
Participant
783 Views
Registered: ‎03-12-2018

Re: Bus Master Enable bit of Endpoint from Rootcomplex

I am using Ultrascale PCIe IP as endpoint. The pg number is 156.

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Xilinx Employee
Xilinx Employee
758 Views
Registered: ‎08-02-2007

回复: Bus Master Enable bit of Endpoint from Rootcomplex

the offset address for the command register is 04 , bit 2 is bus master bit 

The bus number will be decided on the real location of the PCIE hardware 

in the simulation example the address is like this 

  set_add[11] <= #TCQ 28'h0100004; 

Please check   m_axi_ctl_model.v  (in the example design of when you config it as Root Port )  for detailed info

 

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