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nadaumtimuj
Explorer
Explorer
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Registered: ‎01-29-2021

Can anyone help me transitioning from JTAG to PCIe? -- with MATLAB

For a long time, I have been using JTAG for my communication with PC. I used MATLAB JTAG AXI master IP. It was simple to implement but slow. Usually I have a slave register module where I do the read/ write. Here is a screenshot:

nadaumtimuj_0-1627353915462.png

 

 

Now I got a XCU118 board and I want to use PCIe. But MATLAB's PCIe IP seems to be very complicated to me. It has some XDMA ports which I don't know how to wrap. I only need to read/ write from the slave register. Can anyone help me with that transition? Here is a screenshot with PCIe ( I will need to replace the DDR4 with my slave register module):

nadaumtimuj_1-1627354086811.png

 

I have attached the PCIe project. Many thanks.

 

 

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pvenugo
Moderator
Moderator
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Registered: ‎07-31-2012

@nadaumtimuj ,

If you can use the slave register module in screenshot 1 to the second IPI design I guess you would be able to interface it with AXI interconnect , clk and rst.

 

Regards

Praveen


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nadaumtimuj
Explorer
Explorer
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Registered: ‎01-29-2021

@pvenugo Thank you for replying. Two points:

1. Do you think that the attached design will work? MATLAB engineers said their IP only supports KCU116 board for AXI master, and doesn't offer support for VCU118 (they say VCU118 only supports for FIL). That confuses me because both boards have similar pins. If Matlab doesn't work, I don't know what to use for PCIe.

2. The axi_clk is fixed to be 125 MHz by the XDMA IP. Is there a way to drive it with user defined clock?

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