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xujialin1992
Contributor
Contributor
495 Views
Registered: ‎05-20-2015

Can ultrascale change PCIe lane sequence?

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We are going to produce a board with FPGA RFSOC27DR,which has PCIe Interface. However because of the palcement of the PCB, the PCIe Lane has to been revesal form 0~7 to 7~0. I tried to change the PIN map but at last I found it falied. The bitstream is generated with PCIe lane in order,not reversal.

I used to change PCIe channel location in the IP XDC files when I used V7 FPGAs. But I can't found any channel location constrains in Ultrascale PCIe XDC files. The only constrain of PCIe is shown below. Does it mean Ultrascale FPGA cannot change the PCIe lane order?

_______________________________________________

# Add PCIe LOC Constraints Here
#
set_property LOC PCIE40E4_X0Y0 [get_cells pcie_4_0_pipe_inst/pcie_4_0_e4_inst]

_______________________________________________

If I can't change the order, will the  "Set "PL_DISABLE_LANE_REVERSAL" to FALSE" help?

I just want to ensure a RFSOC board PCIe lane can work normally with a lane 7~0 map to PCIe lane 0~7.

 

 

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mmcnicho
Xilinx Employee
Xilinx Employee
442 Views
Registered: ‎10-09-2019

Hi,

For Ultrascale, check the lane reversal section of PG156 to ensure your design supports lane reversal.

If both the advertised and negotiated lane width are x8, I believe lane reversal is supported.

mmcnicho_0-1604006128044.png

 

Let me know if this helps.

Thanks,

Matt

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mmcnicho
Xilinx Employee
Xilinx Employee
443 Views
Registered: ‎10-09-2019

Hi,

For Ultrascale, check the lane reversal section of PG156 to ensure your design supports lane reversal.

If both the advertised and negotiated lane width are x8, I believe lane reversal is supported.

mmcnicho_0-1604006128044.png

 

Let me know if this helps.

Thanks,

Matt

View solution in original post