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Registered: ‎07-08-2019

Configuration PCIe EP

What configuration is expected for DMA/ Bridge Subsytem for PCI express (using example design for simulation) for clock availablility of 100 MHz ( on board ).

Please find the image for reference, AXI Bridge is to be used, as selected in image below,

Question_16aug19.jpg
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

Re: Configuration PCIe EP

Probably the question is not clear. Based on what we see, it should be ok to run a simulation.

Are you running into an issue simulating the generated example design? If you check PG195, it has the details of different options available in the core configuration GUI.

Thanks.

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