What configuration is expected for DMA/ Bridge Subsytem for PCI express (using example design for simulation) for clock availablility of 100 MHz ( on board ).
Please find the image for reference, AXI Bridge is to be used, as selected in image below,
Probably the question is not clear. Based on what we see, it should be ok to run a simulation.
Are you running into an issue simulating the generated example design? If you check PG195, it has the details of different options available in the core configuration GUI.