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174 Views
Registered: ‎10-17-2019

DMA/Bridge subsystem PCIe IP example design

Hi sir,
In example design i kept xilinx DMA/Bridge Subsystem IP at EP side and then RP model is generated in example design so at S_AXI_Lite and S_AXI_B side of EP ip i have connected Microblaze and then i am trying to read in simulation this 0x******00, 0x******10 and 0x******78 register through AXI_LITE interface to write C code for that. But I am not getting rready signal and rdata . 
 
In example design we are writing from RP model to EP side BRAM and then reading back. Now i want to write from EP side through Microblaze interface to using AXI interface. You know through AXI_LITE we can read the configuration registers but i am not able to read it.
 
I tried to write 0xFFFFFFFF on 0x******10h register address and then reading it back. You know to write on BAR0 address FFFFFF we can read range of that address.But i am not getting any value even not getting rready signal high. 
 
I am going to attach my design flow also
Design_ex.png
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4 Replies
Xilinx Employee
Xilinx Employee
121 Views
Registered: ‎08-02-2007

回复: DMA/Bridge subsystem PCIe IP example design

In order to read the RP , the bus master bit in the EP should be enabled 

that is the bit2 of command register  (address 04)

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Visitor rahul090192
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109 Views
Registered: ‎04-29-2019

回复: DMA/Bridge subsystem PCIe IP example design

Have to write at S_Axi_Lite  port na?²

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104 Views
Registered: ‎10-17-2019

回复: DMA/Bridge subsystem PCIe IP example design

sir 0x000-0x12F resgster offset are RO. PG194 page 33. so we can write on 0x04

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98 Views
Registered: ‎10-17-2019

回复: DMA/Bridge subsystem PCIe IP example design

I have tried to write 0xbase_addr+04 address by 0x00000002 value and then tried to read register from 0x00 to 0x21 but not getting anything ..using C code through microblaze at axi_lite port i am trying to read/write. 

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