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Adventurer
Adventurer
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Registered: ‎11-24-2017

DMA Subsystem for PCIe with descriptor bypass - descriptor length

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Hello there,

 

I would like to use DMA Subsystem for PCIe IP core in DMA mode, configured as End Point device with AXI4-Stream interface and descriptor bypass (4-lane Gen 3 PCIe link), as illustrated on image below. My FPGA device is from Zynq Ultrascale+ MPSoC family.

 

                             CSSIF_EP195.png

 

According to PG195 document from April 2018, there are the following IP parameters (among many others):

  • PCIe Max Payload Size that is by default equal to 128B (see Table 2-98 on page 59)
  • User Max Payload Size that is by default equal to 4096B (see Table 2-104 on page 60)
  • Descriptor length parameter that is set through c2h_dsc_byp_len[27:0] interface (max 256MB).

 

Now, if I set Descriptor length parameter to be equal to 8KB, for example, I should be able to send two packets of 4KB per descriptor given that my User Max Payload Size is equal to 4KB. In practice, however, this is not the case. I'm not allowed to send the second 4KB packet (s_axis_c2h_tready_0 always '0') until I re-load the descriptor.

 

Do you have any idea what I am missing here?

 

For your info, here is the set of events I take:

  1. Once PCIe link is UP and configuration is finished, I set the Run bit in control register 0x1004 to enable C2H DMA.
  2. After that I load the descriptor with .c2h_dsc_byp_len_0 = 28'h2000  (8KB)
  3. I wait for s_axis_c2h_tready_0 to be equal to '1' and I send the first 4KB packet through C2H channel.
  4. I wait for s_axis_c2h_tready_0 to be equal to '1' in order to be able to send the second 4KB packet. However, s_axis_c2h_tready_0 is always '0'. I need to re-load descriptor if I want s_axis_c2h_tready_0 to be '1'.

 

Thank you very much for your time and effort.

 

Sincerely,

Bojan.

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Adventurer
Adventurer
1,183 Views
Registered: ‎11-24-2017

Re: DMA Subsystem for PCIe with descriptor bypass - descriptor length

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Hey guys,

I think I found a solution for this issue.

All I needed is to set descriptor bypass length to 8KB and then to send 8KB of AXI-Stream data through C2H channel. DMA PCIe IP takes care of the rest - it cuts 8KB of C2H AXI-Stream data into 2 packets of 4KB each (because user max payload size is by default equal to 4KB).

Cheers,

Bojan.

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Voyager
Voyager
1,390 Views
Registered: ‎05-30-2017

Re: DMA Subsystem for PCIe with descriptor bypass - descriptor length

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Hi @bojankoce,

 

I suggest you to set length = 4KB and to send two separated descriptor if it is not a problem. I also enabled the c2h_sts port of DMA IP because is very usefull. c2h_sts[3] is the strobe in axi clk domain segnaling that descriptor has been executed. Using it I drive DMA in this way:

DMA load descrptor, fpga wait for the ack c2h_sts[3] on dma status port signaling that the descriptor has been executed. The ack reset a timer and after minimum 4 clock cycles I load next descriptor and so on. In my test I observed that without the timer if I load immediately a new descriptor when c2h_sts[3] go High, s_axis_c2h_tready stuck at 0 indefinitely. Probably timer value can also be 2 or 1 but it needs some tests. This is a workaround that I found also if I didn't understand the reason.

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Adventurer
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Registered: ‎11-24-2017

Re: DMA Subsystem for PCIe with descriptor bypass - descriptor length

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Hello @pierlum

 

Thank you very much for your suggestions. I can do it like you proposed (to set length to 4KB and load two separate descriptors). This is my backup solution.

 

I would like though to benefit as much as possible from the possibilities of the IP.

 

I know for c2h_sts port, I already enabled it. For your info, I'm using the polling mode for sending data. This means that I load descriptor, I send the C2H data and I poll C2H status register (0x1004) through AXI4-Lite Slave interface to find out when descriptor is completed. Bits 2, 1, and 0 of that register appear on c2h_sts port also as bits 2, 1, and 0. I also poll C2H channel completed descriptor count register (0x1048) to count the completed descriptors.

 

An alternative to polling mode is to send data in IRQ mode. See page 20 of PG195 document.

 

Sincerely,

Bojan.

 

 

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Adventurer
Adventurer
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Registered: ‎11-24-2017

Re: DMA Subsystem for PCIe with descriptor bypass - descriptor length

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Hey guys,

I think I found a solution for this issue.

All I needed is to set descriptor bypass length to 8KB and then to send 8KB of AXI-Stream data through C2H channel. DMA PCIe IP takes care of the rest - it cuts 8KB of C2H AXI-Stream data into 2 packets of 4KB each (because user max payload size is by default equal to 4KB).

Cheers,

Bojan.

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Observer
Observer
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Registered: ‎12-04-2019

Re: DMA Subsystem for PCIe with descriptor bypass - descriptor length

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Hello

Where and how to write to the descriptor channels? I don't understand how you can write to a register/channel that is not memory mapped. Please explain the procedure to write to these channels.

Regards

 

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