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Advisor pedro_uno
Advisor
2,588 Views
Registered: ‎02-12-2013

Debug Over PCIe - extended config space

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Hello,

 

I have an FPGA in a remote location that I want to debug using XVC talking over PCIe. The Debug Bridge can connect to the PCIe core by AXI or using the extended configuration.  In the past I have put the Debug Bridge on the AXI bus but this time I connected via the extended config port because I want to be able to debug PCIe traffic from software.

 

I also have PR over PCIe enabled in order to do partial reconfiguration remotely.

 

When I run the driver test program I get the following message.  In fact, /dev/xil_xvc/cfg_ioc0 does not exist.

 

$sudo ./driver_test/verify_xil_xvc_driver

Could not open driver at /dev/xil_xvc/cfg_ioc0

Error: No such file or directory

 

I think this is occurring because there is an inconsistency in the extended configuration space.  As I understand it entries in extended config space work like a linked list starting at 0x100.  At 0x100 there is a 12 bit address to the first capability.  That capability has an address to the second and so on. 

 

When I customized the Debug Bridge I told it to be at 0x400.  When I do a hex dump of the ext config space I see the pointer to the first capability which is the MCAP interface for PR at 0x340.  That entry points to address 0x480 however.  The pointer there is 0x000 terminating the list.

 

It looks like the Debug Bridge capability is present at 0x400 but the linked list is broken.  I'm guessing that is why the driver does not give me the device.

 

Does it sound like I am on the right track?  If so, should I fix it by recustomizing the Debug Bridge to be at 0x480?

 

I realize this is very esoteric PCIe stuff but I am hoping someone else has seen this before.

 

  Pete

 

PS: I am using Vivado 2017.4 and driver_v0.4

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Advisor pedro_uno
Advisor
2,906 Views
Registered: ‎02-12-2013

Re: Debug Over PCIe - extended config space

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Beth

Thanks for the hints. I think I understand what is possible and practical for what I am trying to do.

It was shooting high to try to get XDMA, PR over PCIe and Debug over PCIe (XVC) all running in the same multi VU440 platform.  That is essentially what Amazon F1 offers with very deep pockets and (probably) almost infinite Xilinx engineering support.  For one guy alone in a dark lab I'm doing ok.  Here is what I have decided.

XDMA - My processors are PPC running embedded (busybox) LInux so it would be daunting to get this ported to the PPC. Also, additional work would be required to make XDMA compatible with the Xilinx Virtual Cable stuff over PCIe.  Luckily, the PPC chip has substantial native DMA capability well supported by embedded linux.  I can use that to move data.

PR over PCIe - This capability is easy to enable on the Xilinx PCIe bridge.  Software does not require a driver.  There is just a simple "mcap" utility that only depends on the standard pciutils facilities. This should be an easy port to the PPC.

Debug over PCIe - This was the most difficult thing to get working.  The Debug Bridge has a lot of options that affect how things work.  The software requires a driver and an XVC server program that would be difficult to port to PPC running embedded linux.  For now, I am giving up on getting this to work.  Debug will have to be done the old fashioned way using external JTAG cables.

Best regards,

  Pete

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Advisor pedro_uno
Advisor
2,556 Views
Registered: ‎02-12-2013

Re: Debug Over PCIe - extended config space

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OK,

 

I recreated my design with the Debug Bridge (PCIe to BSCAN) set to address 0x480 in extended configuration space. Now when I do the lspci hex dump I see the extended capability linked list setup like this.

 

0x100 -> 0x340 ->0x480 -> 0x000

 

I think 0x340 is PR Over PCIe. 0x480 must be the Debug over PCIe.  Everything is linked correctly but still the device driver is not present at /dev/xil_xvc/cfg_ioc0

 

I am using Ubuntu 16.04 and I followed the driver build and install directions carefully.  Here are the commands I ran.

 

sudo make clean
sudo make install
sudo depmod -a
sudo modprobe -r xil_xvc_driver
sudo modprobe    xil_xvc_driver
dmesg
ls -l /dev/x*
sudo ./driver_test/verify_xil_xvc_driver

 

Any suggestions? 

 

Is this the wrong driver when the Debug Bridge is on the external configuration port of the PCIe?

 

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Advisor pedro_uno
Advisor
2,517 Views
Registered: ‎02-12-2013

Re: Debug Over PCIe - extended config space

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I wrote a little pciutils extended capability scanner.  Everything looks right.

 

$ sudo ./example
0000:02:00.0 vendor=10ee device=8024 class=0700 irq=38 (pin 1) base0=f7000000 (Device 8024)
at 0x100: header = 0x34020001
    at 0x104: header2 = 0x00000000
at 0x340: header = 0x4801000b
    at 0x344: header2 = 0x02c00001
at 0x480: header = 0x0000000b
    at 0x484: header2 = 0x02000008

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Advisor pedro_uno
Advisor
2,502 Views
Registered: ‎02-12-2013

Re: Debug Over PCIe - extended config space

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OK, I just compiled the example design with the VSEC for Debug over PCIe enabled. It gives this for the extended capability linked list:

 

0000:02:00.0 vendor=10ee device=8024 class=0700 irq=38 (pin 1) base0=f7000000 (Device 8024)

at 0x100: header = 0x34020001

    at 0x104: header2 = 0x00000000

at 0x340: header = 0x4801000b

    at 0x344: header2 = 0x02c00001

at 0x480: header = 0x4a00000b

    at 0x484: header2 = 0x01000000

at 0x4a0: header = 0x0000000b

    at 0x4a4: header2 = 0x02000008

 

Unfortunately , loading the driver still does not give me /dev/xil_xvc/cfg_ioc0

 

Now I am beginning to suspect it has something to do with PR over PCIe being enabled at the same time as Debug over PCIe. I'm going to turn off PR over PCIe and try again.

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Advisor pedro_uno
Advisor
2,486 Views
Registered: ‎02-12-2013

Re: Debug Over PCIe - extended config space

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And here is the extended config space with PR over PCIe disabled.

 

0000:02:00.0 vendor=10ee device=8024 class=0700 irq=38 (pin 1) base0=f7000000 (Device 8024)
at 0x100: header = 0x48020001
    at 0x104: header2 = 0x00000000
at 0x480: header = 0x0000000b
    at 0x484: header2 = 0x02000008

 

That is the Debug Bridge there at 0x480.

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Advisor pedro_uno
Advisor
2,463 Views
Registered: ‎02-12-2013

Re: Debug Over PCIe - extended config space

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Ok, now I am trying the Debug Bridge in AXI to BSCAN mode.  I akjusted the AXI offset address in the user .h file, rebuilt and re-installed the driver.  Still it cannot find the Debug Bridge and there is no device in /dev

 

Here is the pcie extended capability space.  Now there is nothing in there.

 

0000:02:00.0 vendor=10ee device=8024 class=0700 irq=38 (pin 1) base0=f7000000 (Device 8024)
at 0x100: header = 0x00020001
    at 0x104: header2 = 0x00000000

 

Can anyone testify that this Debug over PCIe feature really works? 

 

If it does, I must be skipping some step in the process.

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Xilinx Employee
Xilinx Employee
2,446 Views
Registered: ‎12-10-2013

Re: Debug Over PCIe - extended config space

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Hi Pedro,

 

XVC is utilized in several data center applications, so it is definitely usable.  Would it be possible to get your XCI file for the build?  As well, could we get the lspci -xxxxxvvv for the Xilinx device?

 

Sincerely,
Beth

 

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Advisor pedro_uno
Advisor
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Registered: ‎02-12-2013

Re: Debug Over PCIe - extended config space

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Beth,

 

Thanks for the reply.  I've been hacking my design every way possible to find something that makes the driver happy.  I can revert to any those and give you an lspci dump but it looks to me that there is something incompatible in the latest xvc pcie driver code, driver_v0.4. that ships with Vivado 2017.4.

I cloned a Vivado 2017.1 example project from github.  2017.1 ships with driver_v0.3.  I loaded the bitfile from that project, rebooted, compiled and installed the v0.3 driver and it loaded successfully.  It also passed the driver test program in there.

I am running Ubuntu 16.04.  Here is my /proc/version
Linux version 4.4.0-116-generic (buildd@lgw01-amd64-021) (gcc version 5.4.0 20160609 (Ubuntu 5.4.0-6ubuntu1~16.04.9) ) #140-Ubuntu SMP Mon Feb 12 21:23:04 UTC 2018

 

Do you know if the v0.4 driver that ships with 2017.4 runs on Ubuntu?

 

If you see my earlier posts, I checked that the extended capability linked list was correct but the test program, ./driver_test/verify_xil_xvc_driver, never passed.

 

My hardware is down till tomorrow but can you think of anything else to try?

 

  Pete

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Xilinx Employee
Xilinx Employee
2,420 Views
Registered: ‎12-10-2013

Re: Debug Over PCIe - extended config space

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Hi Pete,

 

Please make sure you are set as root, only have the XVC driver attached, and that the driver did actually attach (should show in LSPCI). 

 

Again, if we can get the XCI and lspci, we can run a few checks in house.

 

Thanks!

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Advisor pedro_uno
Advisor
2,404 Views
Registered: ‎02-12-2013

Re: Debug Over PCIe - extended config space

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It sounds like you are suggesting I unload the xdma driver and then see if the xvc driver will connect.  I'll give it a try.

 

I sent my entire design tree with all the XCI files in context via the Xilinx FAE. 

 

Here is the full lspci.

 

$ sudo lspci -s 02:00 -vvvxxxx
[sudo] password for XXXXX:
02:00.0 Serial controller: Xilinx Corporation Device 8024 (prog-if 01 [16450])
    Subsystem: Xilinx Corporation Device 0007
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin A routed to IRQ 38
    Region 0: Memory at f7000000 (32-bit, non-prefetchable) [size=8M]
    Region 1: Memory at f7ef0000 (32-bit, non-prefetchable) [size=64K]
    Capabilities: [80] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
        Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit+
        Address: 00000000fee00000  Data: 40a3
    Capabilities: [c0] Express (v2) Endpoint, MSI 00
        DevCap:    MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
            ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
        DevCtl:    Report errors: Correctable- Non-Fatal+ Fatal+ Unsupported-
            RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
            MaxPayload 256 bytes, MaxReadReq 512 bytes
        DevSta:    CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
        LnkCap:    Port #0, Speed 5GT/s, Width x4, ASPM not supported, Exit Latency L0s unlimited, L1 unlimited
            ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
        LnkCtl:    ASPM Disabled; RCB 64 bytes Disabled- CommClk+
            ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
        LnkSta:    Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
        DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR-, OBFF Not Supported
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
        LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
             Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
             Compliance De-emphasis: -6dB
        LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
             EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
    Capabilities: [100 v2] Advanced Error Reporting
        UESta:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UEMsk:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UESvrt:    DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
        CESta:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
        CEMsk:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
        AERCap:    First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
    Capabilities: [340 v1] Vendor Specific Information: ID=0001 Rev=0 Len=02c <?>
    Capabilities: [480 v0] Vendor Specific Information: ID=0008 Rev=0 Len=020 <?>
    Kernel driver in use: xdma
    Kernel modules: xdma
00: ee 10 24 80 07 04 10 00 00 01 00 07 10 00 00 00
10: 00 00 00 f7 00 00 ef f7 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ee 10 07 00
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Advisor pedro_uno
Advisor
2,031 Views
Registered: ‎02-12-2013

Re: Debug Over PCIe - extended config space

Jump to solution

OK, it looks like there is something I don't understand about the Xilinx xdma and xil_xvc_driver drivers.

 

If I unload the xdma kernel module first I can then run the xil_xvc_driver.  See commands below.

 

I hope this is not a hard limitation since I use the xdma driver to control my FPGA.  I don't think it is possible to unload xdma, load xvc, do debugging, then reload xdma to run software.

 

Is there something I need to do to make these two Xilinx PCIe drivers compatible?

 

$ sudo modprobe -r xdma

$ sudo modprobe -r xil_xvc_driver

$ sudo modprobe     xil_xvc_driver

$ ls -l /dev/xil_xvc/
total 0
crw------- 1 root root 242, 0 Mar 29 12:49 cfg_ioc0

$
$ sudo ./driver_test/verify_xil_xvc_driver
Test Length: 32, 8 us, 4.00 Mbps SUCCESS
XVC PCIE Driver Verified Successfully!

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DSP in hardware and software
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Advisor pedro_uno
Advisor
2,027 Views
Registered: ‎02-12-2013

Re: Debug Over PCIe - extended config space

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OK, now I am trying to connect to the xvc server. Seems to work.

 

$ sudo ./bin/xvc_pcie -s TCP::10200

Enable verbose by setting VERBOSE env var.

Opening /dev/xil_xvc/cfg_ioc0.

 

 

 

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DSP in hardware and software
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Xilinx Employee
Xilinx Employee
2,007 Views
Registered: ‎12-10-2013

Re: Debug Over PCIe - extended config space

Jump to solution

Hi Pete -

 

On the drivers these are provided as reference drivers only.  So we have had many folks combine the functionalities into their driver as a single entity, but that is up to the customer.  (Many also pull in the code needed to drive PR and MCAP as well). 

 

Please post if you need any further assistance, but it looks like having the correct driver attached got you going!

 

Thanks
Beth

 

 

 

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Advisor pedro_uno
Advisor
2,907 Views
Registered: ‎02-12-2013

Re: Debug Over PCIe - extended config space

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Beth

Thanks for the hints. I think I understand what is possible and practical for what I am trying to do.

It was shooting high to try to get XDMA, PR over PCIe and Debug over PCIe (XVC) all running in the same multi VU440 platform.  That is essentially what Amazon F1 offers with very deep pockets and (probably) almost infinite Xilinx engineering support.  For one guy alone in a dark lab I'm doing ok.  Here is what I have decided.

XDMA - My processors are PPC running embedded (busybox) LInux so it would be daunting to get this ported to the PPC. Also, additional work would be required to make XDMA compatible with the Xilinx Virtual Cable stuff over PCIe.  Luckily, the PPC chip has substantial native DMA capability well supported by embedded linux.  I can use that to move data.

PR over PCIe - This capability is easy to enable on the Xilinx PCIe bridge.  Software does not require a driver.  There is just a simple "mcap" utility that only depends on the standard pciutils facilities. This should be an easy port to the PPC.

Debug over PCIe - This was the most difficult thing to get working.  The Debug Bridge has a lot of options that affect how things work.  The software requires a driver and an XVC server program that would be difficult to port to PPC running embedded linux.  For now, I am giving up on getting this to work.  Debug will have to be done the old fashioned way using external JTAG cables.

Best regards,

  Pete

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