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Visitor wraoglter
Visitor
310 Views
Registered: ‎05-16-2018

Dose Xilinx's PCIe IP support soft IP mode?

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Hello all,

 Dose Xilinx's PCIe IP support soft IP mode?

 For example, I want generate xdma IP or qdma IP and I expect Vivado will export PIPE interface to the top module.
 And then I will connect this IP with my design (PIPE PHY). 

I am looking forward to your reply. Thanks!
  

 

1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
258 Views
Registered: ‎08-06-2008

Re: Dose Xilinx's PCIe IP support soft IP mode?

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Hi,

Such a mode is not supported in the tool.

You might be able to extract the IP and the PHY parts of the design and implement as you mentioned after generating the IP. This is not something we have tested or support.

Thanks.

4 Replies
Xilinx Employee
Xilinx Employee
259 Views
Registered: ‎08-06-2008

Re: Dose Xilinx's PCIe IP support soft IP mode?

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Hi,

Such a mode is not supported in the tool.

You might be able to extract the IP and the PHY parts of the design and implement as you mentioned after generating the IP. This is not something we have tested or support.

Thanks.

Visitor wraoglter
Visitor
246 Views
Registered: ‎05-16-2018

Re: Dose Xilinx's PCIe IP support soft IP mode?

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hi,

Thanks for your reply soon.

I assume it is doable. Because we can turn on the option "enable pipe simulation" when generating IP and exportint the example project. I don't think you will create two versions of PCIe upper layer IP for the simulation and systhesis purpose. You seem created a wrapper or something for bring PIPE interface out to the top-level module when we enable the PIPE simualtion. But unfortunatly, in your comments, we cannot know what's the dfference between the simulation IP and systhesis IP, and you also seem cannot guarantee this. 

I think splitint and reomving PHY Layer IP from the xci source may not  be an easy task, we may encounter many compilation issues, such as constraints or others.

Anyway, I will try some simple tests first.
Welcome if you have other suggestion !

Thanks, again.

 

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Xilinx Employee
Xilinx Employee
224 Views
Registered: ‎08-06-2008

Re: Dose Xilinx's PCIe IP support soft IP mode?

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Could you try the following:

  • Enable the External PIPE interface in the GUI
  • Set EXT_PIPE_SIM to TRUE in all occurrences in the files.
  • Comment out synthesis translate_off and synthesis translate_on

I would like to reiterate; this is just for a test and is not an officially supported approach.

Thanks.

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Visitor wraoglter
Visitor
219 Views
Registered: ‎05-16-2018

Re: Dose Xilinx's PCIe IP support soft IP mode?

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Ok! Thank your suggestion.

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