01-01-2012 01:01 PM
which is the easiest way to implement a simple Busmaster DMA (no Scatter Gather) for transfer data from PC to FPGA FIFO memory and from FPGA FIFO memory to PC? I don´t want to use a microblaze processor and I don´t need any memory mapped transfer.
Do I have to use the AXI componenets like AXI DMA? Or should I try to modify the XAPP1052? If I shoud use the xapp1052 where can I implement the fifo interface? I´m not so good in Verilog, so I had to translate the xapp1052 into VHDL first.
Thanks in advance for any answer.
01-01-2012 09:43 PM
01-01-2012 11:45 PM
Thank you for your answer. The central DMA is only for memory mapped access, right? So I have to convert from streaming to memory back to streaming? Hmm....clunky solution. I know, PCIe is never easy, but I will take a look into the EDK components. Are there also reference drivers for using the PCIe with Central DMA? At the moment we use the PEX8311 for PCIe interfacing, but we want to replace this old and clunky chip by native PCIe in FPGA. Also the PEX8311 can run at 3.3V only at the interface and out new design will use the V6, which only can run at 2.5V VCCIO at maximum. This is the background. The second interface on our system is at the moment the Cypress FX2 fur USB HighSpeed and the FX3 for SuperSpeed in the new design.
I took a look into the PLDA DMA core some times ago, but this core is optimized for memory access and may have only very poor performance in FIFO streaming mode. So I will look at NW core...
11-17-2013 08:44 AM
It may not be appropriate to post a question here, but it seems you have the interface between FPGA and PEX 8311 for PCIe communciation(which i am currently working on).
The interface is 32 bit 'C' mode (direct slave). Here the problem is PEX 8311 is driving the FPGA in alternative fashion. For example, when initiated for 4 write or read operation(not in burst), 1st write(suppose) will happen successfully, but at next operation, it seems like PEX has terminated the cycle(address, lbe, ads, blast assert for a clock only and no write-data on bus).
a) Is there a interface problem??(drive, slew, iostandard).
--databus(lvcmos33, slow, 12 mA).
02-07-2020 08:36 AM
I realize that it is 8 years later, but were you able to come up with a solution? I am working on a similar project and any guidance at all would be helpful.