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Visitor
Visitor
8,999 Views
Registered: ‎12-07-2007

Endpoint PIPE for PCI Express: timing issues

Hello everybody,
I'm working on a spartan3(XC3S1500-4 and, in the close future XC3S2000-4)+Endpoint PIPE (v1.7) project.
We have some timing issues with clock signals inside this IP, namely *clk2x and, occasionally, *clkd: the setup slack time for this signals is negative (around -0.5 ns on XC3S1500, while a test on XC3S2000 showed something like -3.5 ns!).
We think that these issues can be the cause of some weird behavior when accessing BAR0 memory from our driver (we perform a lot of accesses and, say 3/4 times in an hour, we get short series of corrupted data. We just perform accesses of 1 word (32 bit) at a time).
So I'm wondering:
* the example given with this IP has constraints for XC3S1000: do they work fine with XC3S1500/XC3S2000? If not, what are the correct settings?
* is there any specific ISE setting that I should take care of for synthesis/implementation?
* Logic utilization is about 93% in the XC3S1500: can this be the source of the problem? If so, how can I solve it?

Thanks in advance!

PS: should I post this message in the Spartan3 forum, too?
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2 Replies
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Xilinx Employee
Xilinx Employee
8,981 Views
Registered: ‎08-07-2007

Re: Endpoint PIPE for PCI Express: timing issues

Hi,

The same constraints shoudl be fine in your device. Not sure what is happening. If you want to post the timing report and your UCF file I will see if anything jumps out.

Regards
John
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Newbie
Newbie
8,977 Views
Registered: ‎12-11-2007

Re: Endpoint PIPE for PCI Express: timing issues

Hi John,
    thank you for your attention.

Please find attached our UCF - I had to filter signals names, hope you don't mind it, but I kept their constraints as they are.
After asking this forum I also tried to relax some of the constraints for the PLM block (I deleted the various LOC, except for BUFGMUX/DCM ones) and run the xplorer script and it seems that the situation has somehow improved (I just got 4 timing errors only), but I'm not sure of what was the change tha gave this improvement. Worst of all, the issue still remains. I'm trying to apply a modification at a time to undestand the situation in a better way. If you can give me some hints, in the meanwhile, that would be highly appreciated!

Here is a sample of the results we get from the static time analysis - just the part with errors (this time clk0 and clk2x).

================================================================================
Timing constraint:
TS_pcie_pipe_BU2_U0_pci_exp_1_lane_epipe_ep0_plm_kh2_mgt_dcm_clk0 = PERIOD     
   TIMEGRP        
"pcie_pipe_BU2_U0_pci_exp_1_lane_epipe_ep0_plm_kh2_mgt_dcm_clk0"        
TS_RXCLK / 2 HIGH 50%;

 12712 items analyzed, 13 timing errors detected. (13 setup errors, 0 hold errors)
 Minimum period is   8.369ns.
--------------------------------------------------------------------------------
Slack:                  -0.369ns (requirement - (data path - clock path skew + uncertainty))
  Source:               pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs_2 (FF)
  Destination:          pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_9 (FF)
  Requirement:          8.000ns
  Data Path Delay:      8.369ns (Levels of Logic = 5)
  Clock Path Skew:      0.000ns
  Source Clock:         pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/mgt_clk rising at 0.000ns
  Destination Clock:    pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/mgt_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs_2 to pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X58Y15.YQ      Tcko                  0.720   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs_2
    SLICE_X59Y15.G1      net (fanout=4)        0.800   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs<2>
    SLICE_X59Y15.Y       Tilo                  0.551   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/com/tlm/u_tlm_tx/vc0/frm_seq/start_retry_tsn_o<7>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/frm/by1_opportunity10
    SLICE_X58Y12.G4      net (fanout=5)        0.426   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/frm/by1_opportunity_map5
    SLICE_X58Y12.Y       Tilo                  0.608   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/tsi/reg_dec5<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>21
    SLICE_X58Y12.F4      net (fanout=4)        0.040   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>_bdd0
    SLICE_X58Y12.X       Tilo                  0.608   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/tsi/reg_dec5<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>11
    SLICE_X52Y10.G1      net (fanout=2)        1.066   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>
    SLICE_X52Y10.Y       Tilo                  0.608   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/tsi/reg_dec6<13>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/sym_gen/sym_sent<6>1
    SLICE_X47Y13.F3      net (fanout=2)        0.734   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sent_status<6>
    SLICE_X47Y13.X       Tilo                  0.551   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/reg_pds_pre<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_or000059
    SLICE_X46Y14.CE      net (fanout=7)        1.055   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_or0000
    SLICE_X46Y14.CLK     Tceck                 0.602   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count<8>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_9
    -------------------------------------------------  ---------------------------
    Total                                      8.369ns (4.248ns logic, 4.121ns route)
                                                       (50.8% logic, 49.2% route)

--------------------------------------------------------------------------------
Slack:                  -0.369ns (requirement - (data path - clock path skew + uncertainty))
  Source:               pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs_2 (FF)
  Destination:          pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_11 (FF)
  Requirement:          8.000ns
  Data Path Delay:      8.369ns (Levels of Logic = 5)
  Clock Path Skew:      0.000ns
  Source Clock:         pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/mgt_clk rising at 0.000ns
  Destination Clock:    pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/mgt_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs_2 to pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X58Y15.YQ      Tcko                  0.720   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs_2
    SLICE_X59Y15.G1      net (fanout=4)        0.800   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs<2>
    SLICE_X59Y15.Y       Tilo                  0.551   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/com/tlm/u_tlm_tx/vc0/frm_seq/start_retry_tsn_o<7>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/frm/by1_opportunity10
    SLICE_X58Y12.G4      net (fanout=5)        0.426   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/frm/by1_opportunity_map5
    SLICE_X58Y12.Y       Tilo                  0.608   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/tsi/reg_dec5<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>21
    SLICE_X58Y12.F4      net (fanout=4)        0.040   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>_bdd0
    SLICE_X58Y12.X       Tilo                  0.608   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/tsi/reg_dec5<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>11
    SLICE_X52Y10.G1      net (fanout=2)        1.066   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>
    SLICE_X52Y10.Y       Tilo                  0.608   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/tsi/reg_dec6<13>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/sym_gen/sym_sent<6>1
    SLICE_X47Y13.F3      net (fanout=2)        0.734   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sent_status<6>
    SLICE_X47Y13.X       Tilo                  0.551   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/reg_pds_pre<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_or000059
    SLICE_X46Y15.CE      net (fanout=7)        1.055   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_or0000
    SLICE_X46Y15.CLK     Tceck                 0.602   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count<10>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_11
    -------------------------------------------------  ---------------------------
    Total                                      8.369ns (4.248ns logic, 4.121ns route)
                                                       (50.8% logic, 49.2% route)

--------------------------------------------------------------------------------
Slack:                  -0.369ns (requirement - (data path - clock path skew + uncertainty))
  Source:               pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs_2 (FF)
  Destination:          pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_10 (FF)
  Requirement:          8.000ns
  Data Path Delay:      8.369ns (Levels of Logic = 5)
  Clock Path Skew:      0.000ns
  Source Clock:         pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/mgt_clk rising at 0.000ns
  Destination Clock:    pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/mgt_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs_2 to pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X58Y15.YQ      Tcko                  0.720   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs_2
    SLICE_X59Y15.G1      net (fanout=4)        0.800   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_outstanding_ccs<2>
    SLICE_X59Y15.Y       Tilo                  0.551   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/com/tlm/u_tlm_tx/vc0/frm_seq/start_retry_tsn_o<7>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/frm/by1_opportunity10
    SLICE_X58Y12.G4      net (fanout=5)        0.426   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/frm/by1_opportunity_map5
    SLICE_X58Y12.Y       Tilo                  0.608   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/tsi/reg_dec5<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>21
    SLICE_X58Y12.F4      net (fanout=4)        0.040   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>_bdd0
    SLICE_X58Y12.X       Tilo                  0.608   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/tsi/reg_dec5<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>11
    SLICE_X52Y10.G1      net (fanout=2)        1.066   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/reg_sym_gen_sel<1>
    SLICE_X52Y10.Y       Tilo                  0.608   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/tsi/reg_dec6<13>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sym/sym_gen/sym_sent<6>1
    SLICE_X47Y13.F3      net (fanout=2)        0.734   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/sent_status<6>
    SLICE_X47Y13.X       Tilo                  0.551   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/reg_pds_pre<0>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_or000059
    SLICE_X46Y15.CE      net (fanout=7)        1.055   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_or0000
    SLICE_X46Y15.CLK     Tceck                 0.602   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count<10>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/fsm/tsx_event_counter1/reg_tx_count_10
    -------------------------------------------------  ---------------------------
    Total                                      8.369ns (4.248ns logic, 4.121ns route)
                                                       (50.8% logic, 49.2% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint:
TS_pcie_pipe_BU2_U0_pci_exp_1_lane_epipe_ep0_plm_kh2_mgt_dcm_clk2x = PERIOD    
    TIMEGRP        
"pcie_pipe_BU2_U0_pci_exp_1_lane_epipe_ep0_plm_kh2_mgt_dcm_clk2x"        
TS_RXCLK HIGH 50%;

 59 items analyzed, 8 timing errors detected. (8 setup errors, 0 hold errors)
 Minimum period is   4.405ns.
--------------------------------------------------------------------------------
Slack:                  -0.405ns (requirement - (data path - clock path skew + uncertainty))
  Source:               pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_pipe_cker (FF)
  Destination:          pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_txdata_7 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.405ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/pipe_clk rising at 0.000ns
  Destination Clock:    pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/pipe_clk rising at 4.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_pipe_cker to pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_txdata_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X70Y0.YQ       Tcko                  0.720   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_pipe_cker
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_pipe_cker
    SLICE_X70Y0.G1       net (fanout=3)        0.614   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_pipe_cker
    SLICE_X70Y0.Y        Tilo                  0.608   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_pipe_cker
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/nstxdata7
    AD21.O1              net (fanout=1)        1.715   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/ns_txdata<7>
    AD21.OTCLK1          Tioock                0.748   txdata<7>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_txdata_7
    -------------------------------------------------  ---------------------------
    Total                                      4.405ns (2.076ns logic, 2.329ns route)
                                                       (47.1% logic, 52.9% route)

--------------------------------------------------------------------------------
Slack:                  -0.296ns (requirement - (data path - clock path skew + uncertainty))
  Source:               pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/scr/reg_tx_char_disp_mode_1 (FF)
  Destination:          pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_txcompliance (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.296ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/mgt_clk rising at 0.000ns
  Destination Clock:    pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/pipe_clk rising at 4.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/scr/reg_tx_char_disp_mode_1 to pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_txcompliance
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X71Y1.XQ       Tcko                  0.720   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/scr/reg_tx_char_disp_mode<1>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/scr/reg_tx_char_disp_mode_1
    SLICE_X71Y0.F2       net (fanout=1)        0.593   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/scr/reg_tx_char_disp_mode<1>
    SLICE_X71Y0.X        Tilo                  0.551   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/ns_txcompliance
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/nstxcompl
    AE23.O1              net (fanout=1)        1.684   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/ns_txcompliance
    AE23.OTCLK1          Tioock                0.748   txcompliance
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_txcompliance
    -------------------------------------------------  ---------------------------
    Total                                      4.296ns (2.019ns logic, 2.277ns route)
                                                       (47.0% logic, 53.0% route)

--------------------------------------------------------------------------------
Slack:                  -0.284ns (requirement - (data path - clock path skew + uncertainty))
  Source:               pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/scr/reg_tx_data_11 (FF)
  Destination:          pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_txdata_3 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.217ns (Levels of Logic = 1)
  Clock Path Skew:      -0.067ns
  Source Clock:         pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/mgt_clk rising at 0.000ns
  Destination Clock:    pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/pipe_clk rising at 4.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/scr/reg_tx_data_11 to pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_txdata_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X65Y1.YQ       Tcko                  0.720   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/scr/reg_tx_data<11>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/scr/reg_tx_data_11
    SLICE_X62Y0.G1       net (fanout=1)        0.580   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/common/scr/reg_tx_data<11>
    SLICE_X62Y0.Y        Tilo                  0.608   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_pipe_ckem
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/nstxdata3
    AE19.O1              net (fanout=1)        1.561   pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/ns_txdata<3>
    AE19.OTCLK1          Tioock                0.748   txdata<3>
                                                       pcie_pipe/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/reg_txdata_3
    -------------------------------------------------  ---------------------------
    Total                                      4.217ns (2.076ns logic, 2.141ns route)
                                                       (49.2% logic, 50.8% route)

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