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Contributor
Contributor
6,379 Views
Registered: ‎02-09-2011

Endpoint with own DDR2 Memory

Moin,

 

I m looking for a reference design for Spartan6, connecting the PCI Express Endpoint Block with a DDR2 Memory. This Memory shall then be visible in the address space of a microcontroller with integrated root complex.So this is in contrast to the usual scenario, where the PCI Endpoint initiates some kind of DMA to the root complex's memory.

Any help, links, pointers to literature, etc.  would be appreciated.

I have here:  The Book: PCI Express System Architecture and in some weeks a sp605 board.

 

Cheers

WK

 

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Xilinx Employee
Xilinx Employee
6,366 Views
Registered: ‎04-06-2010

We have a Virtex-5 application note.  It not Spartan-6, but it may help you get started:

http://www.xilinx.com/support/documentation/application_notes/xapp859.pdf

 

We also have the Spartan-6 Connectivity targeted reference design.  This is talked about in the following links:

http://www.xilinx.com/products/targeted_design_platforms.htm

http://www.nwlogic.com/packetdma/

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Contributor
Contributor
6,346 Views
Registered: ‎02-09-2011

Moin,

 

Thx for the links, seems it's a little bit to big for my needs - x1 with bandwidth < 100MBit/sec will be absolutely sufficient in my case. Here a link, where i stumbled across yesterday; maybe it helps others with the same lack of knowlegde that i still have:

http://www.fpga4fun.com/PCI-Express.html

 

So currently it looks for me like i'd need some state machines understanding and translating the

2 types of TLPs (memory write, memory read) falling out of the PCI-Express component into signals matching the needs of the cmd and write fifos of the DDR2-SDRAM controller component, and setting up a 3rd type of TLP (Completion with data) with output from the read fifo of the SDRAM component.

Am i right, when i think that this should be "all" (haha! :-} ) or am i missing something important?

 

Cheers,

WK

 

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Contributor
Contributor
6,024 Views
Registered: ‎02-09-2011


@derguteweka wrote:
...yadayada...

Am i right, when i think that this should be "all" (haha! :-} ) or am i missing something important?

 


Hello,

 

Just in case somebody else cares:

Meanwhile i can say - Yes, this was "all" -  i'ts up and running.

 

Cheers

WK

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Visitor
Visitor
5,969 Views
Registered: ‎08-01-2011

Hello Derguteweka,

 

Somebody does care :))

Can I ask you some questions?

 

What speed were you able to get?

What was on another side of PCI Express link?

If it was CPU/Linux did you write drivers?

 

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Contributor
Contributor
5,890 Views
Registered: ‎02-09-2011

Hello,

 

OOps, sorry for the late reply; i didnt watch this thread.

* I got awful slow transfer speeds from CPU to the SDRAM attached to the FPGA, approx. 50MBit/sec. But it looks like "the fault" of the CPU, which only does 1 or 2 word transfers. (when executing memcpy function in C). For my application it's fast enough.

* "the other side" of the PCI Express link is an ARM CPU in the GHz class.

* Yes, it's linux and i try to write the driver - still in progress and progress is small..

 

WK

 

 

 

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Visitor
Visitor
5,853 Views
Registered: ‎05-31-2011

Hi derguteweka,

My requirements are the exact same as yours. I need an endpoint design with own DDR2 RAM (ML505). However i am more of a software guy and relatively new to hardware designing. Is it possible to get your working source codes so that i could test it out with appropriate constraints on ml505?

Looking forward to an early response :-)

email id: sks.at.nitr@gmail.com


 

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