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Newbie
Newbie
223 Views
Registered: ‎03-18-2020

Error in block diagram

Please explain what is wrong with this block diagram! Thank you.

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Xilinx Employee
Xilinx Employee
174 Views
Registered: ‎06-13-2018

Hi @C9 ,

Please provide detailed information and also be specific exactly where you are looking the issue. Is it at PCIe side or on the Ethernet side? Please share the screenshot of the error message.
1. First try to create the example design and see, is example design is working or not before jumping to the block design.
2. Check is connecting is correct or not ? If not, please refer to the example design.

3. Which version of Vivado you are using ? 
4. Check the clocking topology. Are you using the correct clock source or not? 

Regards,

Naveen 

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Newbie
Newbie
169 Views
Registered: ‎03-18-2020

Thanks for giving your time.

I actually need to know about the connection of reset of the PCIe. Also, the PCIe should receive clock from the root complex. So I need help regarding this connection too.

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