FPGA reset

[jefin]

FPGA reset is not releasing. fpga keeps the DDR4_reset pin continously low

[drjohnsmith]

Im very happy for you,,,

Im sorry my crystal ball powers have left me today. :->

A bit more information would be of help, like what do you have , what was working, what has worked, what are you doing .

[jefin]

my board is a network interface card and it have two set of DDR each consist of 5 DDR . when powering the board the FPGA keeps set 1's reset pin as active low and set 2's reset pin as active high. so due to this active low state of DDR set 1 the DDR calibration of set 1 becomes fail. and the DDR set 2 have passed the calibration. in order to check whether the reset pin get short with ground, i have uploaded a bit file to toggle the set 1 reset pin as low and high ,and during that time the pin toggled perfectly. i have checked the power and clock signals and that doesn't shows any issues