02-07-2011 07:13 AM
I tried making a GUI based as well as a batch file based implementation of the PCIe EndBlock example design, but came up with this warning in both :
WARNING:PhysDesignRules:372 - Gated clock. Clock net
ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<0> is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
Is this normal? I am a VHDL native, so wasn't able to really trace this icdrreset vector very well (other then find it referenced in pcie_gt_wrapper.v)
Thanks for any help,
02-07-2011 07:28 AM
It's quite normal to get warnings from Xilinx cores. I see the same thing
when using the TEMAC wrapper for V5. Given that the warning is pointing
to a file well down the hierarchy inside the endpoint block, I'd say you
can ignore it. It should not mean you hooked up the core incorrectly.