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nugentoffer
Contributor
Contributor
4,008 Views
Registered: ‎10-27-2010

Gated Clock when implementing example PIO design

Hello,

 

I tried making a GUI based as well as a batch file based implementation of the PCIe EndBlock example design, but came up with this warning in both :

 

WARNING:PhysDesignRules:372 - Gated clock. Clock net
   ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<0> is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.

 

 

Is this normal? I am a VHDL native, so wasn't able to really trace this icdrreset vector very well (other then find it referenced in pcie_gt_wrapper.v)

 

Thanks for any help,

N

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2 Replies
gszakacs
Professor
Professor
4,005 Views
Registered: ‎08-14-2007

It's quite normal to get warnings from Xilinx cores.  I see the same thing

when using the TEMAC wrapper for V5.  Given that the warning is pointing

to a file well down the hierarchy inside the endpoint block, I'd say you

can ignore it.  It should not mean you hooked up the core incorrectly.

 

-- Gabor

-- Gabor
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jayer
Xilinx Employee
Xilinx Employee
3,988 Views
Registered: ‎08-07-2007

Hi,

 

Yes, this warning is expected with the core and you can ignore it.

 

Regards

John

 

 

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