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Observer
Observer
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Registered: ‎10-30-2018

Has the PCIe Gen4 RP IP been tested in Xilinx Lab?

I learned that the VCU128 EVB is the only available PCIe Gen4 EVB from Xilinx, but it only supports the PCIe Gen4 EP IP test, and not for PCIe Gen4 RP. 

Now we are trying to build a PCIe Gen4 RP port on the VCU128 EVB FMC+ connector, to drive a PCIe Gen4 device daughter card plugged on it. We built a PCIE RP Gen4 x4 IP in FPGA connected to the FMC+, and I am testing the PCIe RP Gen4 X4 connection using the Vivado created design example, but failed in the initial Gen4 rate link up test.  (The Gen3 rate link up is working without issue).

There are number of issues found in doing it,

1) When creating the PCIe RP Gen4 x4 IP, both simulation and synthesis are failed in the created design example folder. I found number of code errors (missing port connections) need to be fixed manually to make the simulation and synthesis work.

2) The VCU128 EVB FPGA does not have the dedicated PCIe RP port connection, but the PCIe RP IP creating wizard assigns the transceiver location in wrong bank (does not match with the GUI GTY selection). The worst thing is that the embedded IBERT debug core location is assigned in wrong bank too, which user cannot correct (it is read-only under the RP IP wrapper).

3) In the lab testing, I found that in Gen4 rate link up training, the RP Equalization Phase-3 control looks not right (FPGA RP IP is the master in EQ3). After the LTSSM entered the EQ3 state, the 130b/128b decode error shows up frequently, and then failed EQ3 eventually. Is it reasonable? (It already passed EQ1 tuning and had one working setting?)

4) In doing the FMC+ daughter card design, we found that the differential pair trace between FPGA and FMC+ on VCU128 EVB has large length mismatch. (I have reported it before in https://forums.xilinx.com/t5/Evaluation-Boards/VCU128-EVB-FPGA-GTY-to-FMC-connection-has-poor-PCB-layout-design/td-p/983798) so no matter how we do length mismatch compensation in the daughter card design, the PCIe link trace layout cannot be good as required, which could cause the issue in 3).

5) The PCIe RP IP creating wizard has only few options in the GTY setting tab to allow user to vary. No matter what I changed in these option selecting, the link equalization behavior at Gen4 rate does not improve.

I would like to know if Xilinx has tested the PCIe Gen4 RP IP in their lab or not? (It looks like the Gen4 RP IP created from Vivado v2019.1.2 has not been tested yet). If anyone from Xilinx Ultrascale+ PCIe RP debug/test team can help in solving our PCIe Gen4 RP connection issue?

Thanks,

Xiao

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Moderator
Moderator
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Registered: ‎01-15-2008

Hi wangxiao@skhms ,

 

We are working on this PCIe Gen4 RP IP isssue internally and will update once there is progress.

thanks

Krishna

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