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10-09-2019 11:16 PM
Hi Xilinx Support Team,
My design include 3 PCIe IP like picture in below. I use XCKU11P-FFVA1156-1-e FPGA chip.
10-10-2019 06:04 AM
Hello @hoavo95_greystone
I don't think your usecase is implementable on your device.
Please use a separate REFCLK pins.
Please see also PG213 Table 102
https://www.xilinx.com/support/documentation/ip_documentation/pcie4_uscale_plus/v1_3/pg213-pcie4-ultrascale-plus.pdf
This table shows that your device has only 4 PCIE blocks. (Half of them are placed on different side of the device ). Perhaps you can use a single REFCLK pins for PCIe blocks on "X0Y3 and X0Y2", but you will need another REFCLK pin (+IBUFDS_GTE4) for "X1Y0 and X1Y1"
Hope this helps.
Thanks & regards
Leo
10-10-2019 06:04 AM
Hello @hoavo95_greystone
I don't think your usecase is implementable on your device.
Please use a separate REFCLK pins.
Please see also PG213 Table 102
https://www.xilinx.com/support/documentation/ip_documentation/pcie4_uscale_plus/v1_3/pg213-pcie4-ultrascale-plus.pdf
This table shows that your device has only 4 PCIE blocks. (Half of them are placed on different side of the device ). Perhaps you can use a single REFCLK pins for PCIe blocks on "X0Y3 and X0Y2", but you will need another REFCLK pin (+IBUFDS_GTE4) for "X1Y0 and X1Y1"
Hope this helps.
Thanks & regards
Leo
10-21-2019 05:18 PM
Hi
I am planning the same for my board.
Is this issue solved ? Is there any other workaound instead of using separated input clock pins ?
Best regards
10-23-2019 12:41 AM
Hello @hoavo95_greystone
If your question is already answered
Could you please kindly marked this thread as Solved ? , so other Forum user can learn from your experience.
Hello @yuko.2828
No, This constraint is device limitation, there is no workaround for this.
BTW next time, Could you please post a new question rather than adding your question to
the other person thread. It may bring some confussion for other user reading this post.
Thanks
Leo