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Registered: ‎01-21-2019

Help with BUFDS_GTE4 in Ultrascale+.

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Hi Xilinx Support Team,

My design include 3 PCIe IP like picture in below. I use XCKU11P-FFVA1156-1-e FPGA chip.

Capture.PNG

I use 1 BUFDS_GTE4 to driven clock for 3 PCIe IP blocks. I compile synthesis pass but compile implementation fails and I get this error:
 
[DRC REQP-1963] connects_too_many_BUFG_GT_SYNC_loads: The IBUFDS_GTE4 refclk_ibuf (ODIV2 pin) is driving more than one BUFG_GT_SYNC load, which is an unroutable situation. Optimization may not have been able to merge BUFG_GT_SYNC cells because of differing control pin connections.
 
Can you please help me fix this issue ?
Thank you so much.
 
Regards,
HoaVo
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Xilinx Employee
Xilinx Employee
503 Views
Registered: ‎03-30-2016

Hello @hoavo95_greystone 


I don't think your usecase is implementable on your device.
Please use a separate REFCLK pins.

Please see also PG213 Table 102
https://www.xilinx.com/support/documentation/ip_documentation/pcie4_uscale_plus/v1_3/pg213-pcie4-ultrascale-plus.pdf
KU11P_PCIe.png

This table shows that your device has only 4 PCIE blocks. (Half of them are placed on different side of the device ). Perhaps you can use a single REFCLK pins for PCIe blocks on "X0Y3 and X0Y2", but you will need another REFCLK pin (+IBUFDS_GTE4) for "X1Y0 and X1Y1"

Hope this helps.

Thanks & regards
Leo

 

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Xilinx Employee
Xilinx Employee
504 Views
Registered: ‎03-30-2016

Hello @hoavo95_greystone 


I don't think your usecase is implementable on your device.
Please use a separate REFCLK pins.

Please see also PG213 Table 102
https://www.xilinx.com/support/documentation/ip_documentation/pcie4_uscale_plus/v1_3/pg213-pcie4-ultrascale-plus.pdf
KU11P_PCIe.png

This table shows that your device has only 4 PCIE blocks. (Half of them are placed on different side of the device ). Perhaps you can use a single REFCLK pins for PCIe blocks on "X0Y3 and X0Y2", but you will need another REFCLK pin (+IBUFDS_GTE4) for "X1Y0 and X1Y1"

Hope this helps.

Thanks & regards
Leo

 

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Adventurer
Adventurer
441 Views
Registered: ‎12-27-2018

Hi

I am planning the same for my board.

Is this issue solved ? Is there any other workaound instead of using separated input clock pins ?

 

Best regards

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Xilinx Employee
Xilinx Employee
398 Views
Registered: ‎03-30-2016

Hello @hoavo95_greystone 

If your question is already answered
Could you please kindly marked this thread as Solved ? , so other Forum user can learn from your experience.

Hello @yuko.2828 

No, This constraint is device limitation, there is no workaround for this.
BTW next time, Could you please post a new question rather than adding your question to
the other person thread. It may bring some confussion for other user reading this post.


Thanks
Leo

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