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renbit
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Registered: ‎06-18-2017

How Set CRC Check for the PCIe V3.3

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Hi

I want check if communication data is wrong or not for the IP Core PCIe V3.3. I get some information from pg054 published in the 2017. But I can’t find that RECRC Check in the PCIe V3.3 configuration page.

My question:

  1. How I config for the ERCR check enable, Who can give me some advice;
  2. If I want to check transmitted data is succeed or not, what am I gonna do.

Who can give me some advice, thank you.

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PCI-E Config.png
PCIe_RECRC.png
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hpoetzl
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Registered: ‎06-24-2013

Hey @renbit,

 

I try to search the parameter RECRC_CHECK or singal, but I can't get it.

This is part of the DRP where it is called RECRC_CHK[1:0] (similar with the RECRC_CHK_TRIM)

There is also some information on page 229 which suggests that:

  • 0 = Do not check
  • 1 = Always check
  • 3 = Check if enabled in the AER

If I want to know the data is transmitted to other pcie device is succeed or not ,what should I do?

This is something the ECRC cannot do. All you can do on the transmit side is decide whether you want the ECRC or not (via TRNTECRCGEN) - at least that's how I understand it.

 

Best,

Herbert

-------------- Yes, I do this for fun!

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hpoetzl
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Registered: ‎06-24-2013

Hey @renbit,

 

How I config for the ERCR check enable?

Most likely by setting the RECRC_CHECK to something greater than 0.

 

If I want to check transmitted data is succeed or not, what am I gonna do?

The PCIe v3.3 IP has an output called TRNRECRCERR which when asserted (at EOF), indicates that the current packet in progress has an ECRC error.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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renbit
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Registered: ‎06-18-2017
Hi,@hpoetzl, thank you for your information.   How I config for the ERCR check enable? Most likely by setting the RECRC_CHECK to something greater than 0. //////But I can't find RECRC_CHECK in the IP Core or PCI-e  example project code. I try to search the parameter RECRC_CHECK   or singal, but I can't get it.   If I want to check transmitted data is succeed or not, what am I gonna do? The PCIe v3.3 IP has an output called TRNRECRCERR which when asserted (at EOF), indicates that the current packet in progress has an ECRC error.  /////I guess that the signal TRNRECRCERR  may be same as rx_ecrc_err(or m_axis_rx_tuser[0]). It indicates that received data is right or not in the PCIe Core. If I want to know the data is transmitted to other pcie device is succeed or not ,what should I do, thank you very much.
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hpoetzl
Voyager
Voyager
5,949 Views
Registered: ‎06-24-2013

Hey @renbit,

 

I try to search the parameter RECRC_CHECK or singal, but I can't get it.

This is part of the DRP where it is called RECRC_CHK[1:0] (similar with the RECRC_CHK_TRIM)

There is also some information on page 229 which suggests that:

  • 0 = Do not check
  • 1 = Always check
  • 3 = Check if enabled in the AER

If I want to know the data is transmitted to other pcie device is succeed or not ,what should I do?

This is something the ECRC cannot do. All you can do on the transmit side is decide whether you want the ECRC or not (via TRNTECRCGEN) - at least that's how I understand it.

 

Best,

Herbert

-------------- Yes, I do this for fun!

View solution in original post

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renbit
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Registered: ‎06-18-2017
@hpoetzl  I get that how configuring parameters for ECRC_CHECK for V3.3. I should select the Advanced mode in the Basic tab ,then I find that the RECRC Check in the Ext Capabilities-2 tab. Thank you for your advice. PS. How do you use @ somebody and change the  character form in the reply. 
PCI-E ConfigV3.3.png
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balkris
Xilinx Employee
Xilinx Employee
3,916 Views
Registered: ‎08-01-2008

check page number 75
https://www.xilinx.com/support/documentation/ip_documentation/pcie_7x/v3_3/pg054-7series-pcie.pdf

Using ECRC Generation (128-Bit Interface)
The integrated block supports automatic ECRC generation. To enable this feature, the user
application must assert (tx_ecrc_gen) s_axis_tx_tuser[0] at the beginning of a
TLP on the transmit AXI4-Stream interface. This signal can be asserted through the duration
of the packet, if desired. If the outgoing TLP does not already have a digest, the core
generates and appends one and sets the TD bit. There is a single-clock cycle deassertion of
s_axis_tx_tready at the end of packet to allow for insertion of the digest. Figure 3-41
illustrates ECRC generation operation.

 

check this related post as well

https://forums.xilinx.com/t5/PCI-Express/ECRC-Question-of-7-Series-FPGAs-Integrated-Block-for-PCI-Express/td-p/495812

Thanks and Regards
Balkrishan
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